Lines Matching refs:inx
114695 This commit fixes how instructions are masked on Zhinx+Z{d,q}inx.
158513 RISC-V: Add testcases for z[fdq]inx
158515 instructions that reuse by z[fdq]inx.
158530 RISC-V: Add instructions and operand set for z[fdq]inx
158532 verify if z*inx enabled and use gpr instead of fpr when z*inx is enable.
158537 z*inx extension.
158541 * config/tc-riscv.c (riscv_ip): Added register choice for z*inx.
158545 * opcode/riscv.h (enum riscv_insn_class): Reused INSN_CLASS_* for z*inx.
158550 z*inx.
158551 * riscv-opc.c: Reused INSN_CLASS_* for z*inx.
158557 RISC-V: Add mininal support for z[fdq]inx
158565 for z*inx extensions.
158566 (riscv_supported_std_z_ext): Added entries for z*inx.
158567 (riscv_parse_check_conflicts): Added conflict check for z*inx.