Lines Matching refs:IVSigned

2594   const bool IVSigned = IVExpr->getType()->hasSignedIntegerRepresentation();  in EmitOMPOuterLoop()  local
2618 RT.emitForNext(*this, S.getBeginLoc(), IVSize, IVSigned, LoopArgs.IL, in EmitOMPOuterLoop()
2659 [&S, &LoopArgs, LoopExit, &CodeGenLoop, IVSize, IVSigned, &CodeGenOrdered, in EmitOMPOuterLoop()
2672 [IVSize, IVSigned, Loc, &CodeGenOrdered](CodeGenFunction &CGF) { in EmitOMPOuterLoop()
2673 CodeGenOrdered(CGF, Loc, IVSize, IVSigned); in EmitOMPOuterLoop()
2768 const bool IVSigned = IVExpr->getType()->hasSignedIntegerRepresentation(); in EmitOMPForOuterLoop() local
2778 IVSigned, Ordered, DipatchRTInputValues); in EmitOMPForOuterLoop()
2781 IVSize, IVSigned, Ordered, LoopArgs.IL, LoopArgs.LB, LoopArgs.UB, in EmitOMPForOuterLoop()
2789 const bool IVSigned) { in EmitOMPForOuterLoop() argument
2792 IVSigned); in EmitOMPForOuterLoop()
2808 const unsigned IVSize, const bool IVSigned) {} in emitEmptyOrdered() argument
2824 const bool IVSigned = IVExpr->getType()->hasSignedIntegerRepresentation(); in EmitOMPDistributeOuterLoop() local
2827 IVSize, IVSigned, /* Ordered = */ false, LoopArgs.IL, LoopArgs.LB, in EmitOMPDistributeOuterLoop()
3156 const bool IVSigned = IVExpr->getType()->hasSignedIntegerRepresentation(); in EmitOMPWorksharingLoop() local
3188 [IVSize, IVSigned, Ordered, IL, LB, UB, ST, StaticChunkedOne, Chunk, in EmitOMPWorksharingLoop()
3197 IVSize, IVSigned, Ordered, IL.getAddress(CGF), in EmitOMPWorksharingLoop()
5135 const bool IVSigned = IVExpr->getType()->hasSignedIntegerRepresentation(); in EmitOMPDistributeLoop() local
5152 IVSize, IVSigned, /* Ordered = */ false, IL.getAddress(*this), in EmitOMPDistributeLoop()