Lines Matching defs:SrcOps

4462   SmallVector<SDValue> SrcOps(Ops);
4463   for (SDValue &Op : SrcOps) {
4480   SDValue Res = DAG.getNode(Opcode, DL, DstVT, SrcOps);
22603                                  SmallVectorImpl<SDValue> &SrcOps,
22646       SrcOps.push_back(Src);
22658     for (SDValue &SrcOp : SrcOps)
40745     ArrayRef<SDValue> SrcOps, int SrcOpIndex, SDValue Root,
40764   SDValue Op = SrcOps[SrcOpIndex];
40877     Ops.append(SrcOps.begin(), SrcOps.end());
51096   // TODO: Support multiple SrcOps.
51098     SmallVector<SDValue, 2> SrcOps;
51100     if (matchScalarReduction(SDValue(N, 0), ISD::AND, SrcOps, &SrcPartials) &&
51101         SrcOps.size() == 1) {
51102       unsigned NumElts = SrcOps[0].getValueType().getVectorNumElements();
51104       SDValue Mask = combineBitcastvxi1(DAG, MaskVT, SrcOps[0], dl, Subtarget);
51105       if (!Mask && TLI.isTypeLegal(SrcOps[0].getValueType()))
51106         Mask = DAG.getBitcast(MaskVT, SrcOps[0]);
51904   // TODO: Support multiple SrcOps.
51906     SmallVector<SDValue, 2> SrcOps;
51908     if (matchScalarReduction(SDValue(N, 0), ISD::OR, SrcOps, &SrcPartials) &&
51909         SrcOps.size() == 1) {
51910       unsigned NumElts = SrcOps[0].getValueType().getVectorNumElements();
51912       SDValue Mask = combineBitcastvxi1(DAG, MaskVT, SrcOps[0], dl, Subtarget);
51913       if (!Mask && TLI.isTypeLegal(SrcOps[0].getValueType()))
51914         Mask = DAG.getBitcast(MaskVT, SrcOps[0]);
53194     SmallVector<SDValue, 2> SrcOps;
53197     if (getTargetShuffleInputs(BC, SrcOps, SrcMask, DAG) &&
53198         !isAnyZero(SrcMask) && all_of(SrcOps, [BC](SDValue Op) {
53201       resolveTargetShuffleInputsAndMask(SrcOps, SrcMask);
53202       if (!UseSubVector && SrcOps.size() <= 2 &&
53204         N0 = !SrcOps.empty() ? SrcOps[0] : SDValue();
53205         N1 = SrcOps.size() > 1 ? SrcOps[1] : SDValue();
53208       if (UseSubVector && SrcOps.size() == 1 &&
53210         std::tie(N0, N1) = DAG.SplitVector(SrcOps[0], SDLoc(Op));