Lines Matching defs:PVT

7008     EVT PVT = LD->getValueType(0);
7009     if (PVT != MVT::i32 && PVT != MVT::f32)
7060     EVT NVT = EVT::getVectorVT(*DAG.getContext(), PVT, NumElems);
7580       MVT PVT = TLI.getPointerTy(DAG.getDataLayout());
7586         SDValue CP = DAG.getConstantPool(C, PVT);
7602         SDValue VCP = DAG.getConstantPool(VecC, PVT);
15225   MVT PVT = VT.isFloatingPoint() ? MVT::v4f64 : MVT::v4i64;
15226   SDValue Flipped = DAG.getBitcast(PVT, V1);
15228       DAG.getVectorShuffle(PVT, DL, Flipped, DAG.getUNDEF(PVT), {2, 3, 0, 1});
36580   MVT PVT = getPointerTy(MF->getDataLayout());
36581   const TargetRegisterClass *PtrRC = getRegClassFor(PVT);
36583   unsigned XorRROpc = (PVT == MVT::i64) ? X86::XOR64rr : X86::XOR32rr;
36591   unsigned RdsspOpc = (PVT == MVT::i64) ? X86::RDSSPQ : X86::RDSSPD;
36595   unsigned PtrStoreOpc = (PVT == MVT::i64) ? X86::MOV64mr : X86::MOV32mr;
36597   const int64_t SSPOffset = 3 * PVT.getStoreSize();
36638   MVT PVT = getPointerTy(MF->getDataLayout());
36639   assert((PVT == MVT::i64 || PVT == MVT::i32) &&
36677   const int64_t LabelOffset = 1 * PVT.getStoreSize();
36683     PtrStoreOpc = (PVT == MVT::i64) ? X86::MOV64mr : X86::MOV32mr;
36684     const TargetRegisterClass *PtrRC = getRegClassFor(PVT);
36703     PtrStoreOpc = (PVT == MVT::i64) ? X86::MOV64mi32 : X86::MOV32mi;
36780   MVT PVT = getPointerTy(MF->getDataLayout());
36781   const TargetRegisterClass *PtrRC = getRegClassFor(PVT);
36834   if (PVT == MVT::i64) {
36845   unsigned RdsspOpc = (PVT == MVT::i64) ? X86::RDSSPQ : X86::RDSSPD;
36850   unsigned TestRROpc = (PVT == MVT::i64) ? X86::TEST64rr : X86::TEST32rr;
36862   unsigned PtrLoadOpc = (PVT == MVT::i64) ? X86::MOV64rm : X86::MOV32rm;
36863   const int64_t SPPOffset = 3 * PVT.getStoreSize();
36880   unsigned SubRROpc = (PVT == MVT::i64) ? X86::SUB64rr : X86::SUB32rr;
36893   unsigned ShrRIOpc = (PVT == MVT::i64) ? X86::SHR64ri : X86::SHR32ri;
36894   unsigned Offset = (PVT == MVT::i64) ? 3 : 2;
36901   unsigned IncsspOpc = (PVT == MVT::i64) ? X86::INCSSPQ : X86::INCSSPD;
36918   unsigned ShlR1Opc = (PVT == MVT::i64) ? X86::SHL64ri : X86::SHL32ri;
36926   unsigned MovRIOpc = (PVT == MVT::i64) ? X86::MOV64ri32 : X86::MOV32ri;
36945   unsigned DecROpc = (PVT == MVT::i64) ? X86::DEC64r : X86::DEC32r;
36969   MVT PVT = getPointerTy(MF->getDataLayout());
36970   assert((PVT == MVT::i64 || PVT == MVT::i32) &&
36974     (PVT == MVT::i64) ? &X86::GR64RegClass : &X86::GR32RegClass;
36978   Register FP = (PVT == MVT::i64) ? X86::RBP : X86::EBP;
36983   const int64_t LabelOffset = 1 * PVT.getStoreSize();
36984   const int64_t SPOffset = 2 * PVT.getStoreSize();
36986   unsigned PtrLoadOpc = (PVT == MVT::i64) ? X86::MOV64rm : X86::MOV32rm;
36987   unsigned IJmpOpc = (PVT == MVT::i64) ? X86::JMP64r : X86::JMP32r;
37051   MVT PVT = getPointerTy(MF->getDataLayout());
37052   assert((PVT == MVT::i64 || PVT == MVT::i32) && "Invalid Pointer Size!");
37061     Op = (PVT == MVT::i64) ? X86::MOV64mi32 : X86::MOV32mi;
37064         (PVT == MVT::i64) ? &X86::GR64RegClass : &X86::GR32RegClass;
37066     Op = (PVT == MVT::i64) ? X86::MOV64mr : X86::MOV32mr;
42080         MVT PVT = TLI.getPointerTy(DAG.getDataLayout());
42081         SDValue CP = DAG.getConstantPool(ConstantVector::get(ConstantVec), PVT);
58063       MVT PVT = TLI.getPointerTy(DAG.getDataLayout());
58064       SDValue CV = DAG.getConstantPool(C, PVT);
59640 bool X86TargetLowering::IsDesirableToPromoteOp(SDValue Op, EVT &PVT) const {
59733   PVT = MVT::i32;