Lines Matching defs:Signed

1567 HexagonTargetLowering::resizeToWidth(SDValue VecV, MVT ResTy, bool Signed,
1587     unsigned ExtOpc = Signed ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
1590     unsigned NarOpc = Signed ? HexagonISD::SSAT : HexagonISD::USAT;
2401       const SDLoc &dl, bool Signed, SelectionDAG &DAG) const {
2408   if (!Signed) {
2416   // Signed overflow has happened, if:
2432       bool Signed, SelectionDAG &DAG) const {
2453   unsigned ShRight = Signed ? ISD::SRA : ISD::SRL;
2463   auto [Tmp0, Ovf] = emitHvxAddWithOverflow(Inp, LowBits, dl, Signed, DAG);
2588     assert(SignedB && "Signed A and unsigned B should have been inverted");
2634     assert(!SignedA && "Signed A and unsigned B should have been inverted");
2689   bool Signed = Opc == ISD::FP_TO_SINT || Opc == ISD::SINT_TO_FP;
2692   SDValue WInp = resizeToWidth(Inp, WInpTy, Signed, dl, DAG);
2694   SDValue Res = resizeToWidth(Conv, ResTy, Signed, dl, DAG);
2864   bool Signed = Opc == ISD::SINT_TO_FP;
2872   SDValue Abs = Signed ? DAG.getNode(ISD::ABS, dl, InpTy, Op0) : Op0;
2878   if (Signed) {