Lines Matching refs:Entry
184 bool VerifyPredAndCC(MachineInstr *MI, const ReduceEntry &Entry,
189 const ReduceEntry &Entry);
192 const ReduceEntry &Entry, bool LiveCPSR, bool IsSelfLoop);
197 const ReduceEntry &Entry, bool LiveCPSR,
203 const ReduceEntry &Entry, bool LiveCPSR,
328 Thumb2SizeReduce::VerifyPredAndCC(MachineInstr *MI, const ReduceEntry &Entry,
331 if ((is2Addr && Entry.PredCC2 == 0) ||
332 (!is2Addr && Entry.PredCC1 == 0)) {
351 } else if ((is2Addr && Entry.PredCC2 == 2) ||
352 (!is2Addr && Entry.PredCC1 == 2)) {
401 const ReduceEntry &Entry) {
410 unsigned Opc = Entry.NarrowOpc1;
412 uint8_t ImmLimit = Entry.Imm1Limit;
414 switch (Entry.WideOpc) {
420 Opc = Entry.NarrowOpc2;
421 ImmLimit = Entry.Imm2Limit;
462 bool IsStore = Entry.WideOpc == ARM::t2STR_POST;
476 auto MIB = BuildMI(MBB, MI, dl, TII->get(Entry.NarrowOpc1))
536 Opc = Entry.NarrowOpc2; // tPOP_RET
548 (Entry.WideOpc == ARM::t2LDMIA_UPD ||
549 Entry.WideOpc == ARM::t2STMDB_UPD)) {
550 Opc = Entry.NarrowOpc2; // tPOP or tPUSH
553 (Entry.WideOpc != ARM::t2LDMIA_UPD &&
554 Entry.WideOpc != ARM::t2STMIA_UPD)) {
592 if (Entry.WideOpc == ARM::t2STMIA)
629 const ReduceEntry &Entry,
636 if (ReduceTo2Addr(MBB, MI, Entry, LiveCPSR, IsSelfLoop))
638 return ReduceToNarrow(MBB, MI, Entry, LiveCPSR, IsSelfLoop);
675 if (Entry.LowRegs1 && !VerifyLowRegs(MI))
679 return ReduceLoadStore(MBB, MI, Entry);
690 if (ReduceTo2Addr(MBB, MI, Entry, LiveCPSR, IsSelfLoop))
694 return ReduceToNarrow(MBB, MI, Entry, LiveCPSR, IsSelfLoop);
706 return ReduceToNarrow(MBB, MI, Entry, LiveCPSR, IsSelfLoop);
712 return ReduceToNarrow(MBB, MI, Entry, LiveCPSR, IsSelfLoop);
724 return ReduceToNarrow(MBB, MI, Entry, LiveCPSR, IsSelfLoop);
734 return ReduceToNarrow(MBB, MI, Entry, LiveCPSR, IsSelfLoop);
742 const ReduceEntry &Entry,
747 if (!OptimizeSize && Entry.AvoidMovs && STI->avoidMOVsShifterOperand())
786 if (Entry.LowRegs2 && !isARMLowRegister(Reg0))
788 if (Entry.Imm2Limit) {
790 unsigned Limit = (1 << Entry.Imm2Limit) - 1;
795 if (Entry.LowRegs2 && !isARMLowRegister(Reg2))
800 const MCInstrDesc &NewMCID = TII->get(Entry.NarrowOpc2);
821 if (!VerifyPredAndCC(MI, Entry, true, Pred, LiveCPSR, HasCC, CCDead))
826 if (Entry.PartFlag && NewMCID.hasOptionalDef() && HasCC &&
860 const ReduceEntry &Entry,
865 if (!OptimizeSize && Entry.AvoidMovs && STI->avoidMOVsShifterOperand())
871 if (Entry.Imm1Limit)
872 Limit = (1 << Entry.Imm1Limit) - 1;
883 if (Entry.LowRegs1 && !isARMLowRegister(Reg))
892 const MCInstrDesc &NewMCID = TII->get(Entry.NarrowOpc1);
912 if (!VerifyPredAndCC(MI, Entry, false, Pred, LiveCPSR, HasCC, CCDead))
917 if (Entry.PartFlag && NewMCID.hasOptionalDef() && HasCC &&
1022 const ReduceEntry &Entry = ReduceTable[OPI->second];
1025 if (Entry.Special)
1026 return ReduceSpecial(MBB, MI, Entry, LiveCPSR, IsSelfLoop);
1029 if (Entry.NarrowOpc2 &&
1030 ReduceTo2Addr(MBB, MI, Entry, LiveCPSR, IsSelfLoop))
1034 if (Entry.NarrowOpc1 &&
1035 ReduceToNarrow(MBB, MI, Entry, LiveCPSR, IsSelfLoop))