Lines Matching defs:MI
79 uint64_t getBinaryCodeForInstr(const MCInst &MI,
85 unsigned getMachineOpValue(const MCInst &MI,const MCOperand &MO,
93 uint32_t getHiLoImmOpValue(const MCInst &MI, unsigned OpIdx,
97 bool EncodeAddrModeOpValues(const MCInst &MI, unsigned OpIdx,
104 uint32_t getThumbBLTargetOpValue(const MCInst &MI, unsigned OpIdx,
110 uint32_t getThumbBLXTargetOpValue(const MCInst &MI, unsigned OpIdx,
115 uint32_t getThumbBRTargetOpValue(const MCInst &MI, unsigned OpIdx,
120 uint32_t getThumbBCCTargetOpValue(const MCInst &MI, unsigned OpIdx,
125 uint32_t getThumbCBTargetOpValue(const MCInst &MI, unsigned OpIdx,
131 uint32_t getBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,
137 uint32_t getThumbBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,
143 uint32_t getARMBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,
146 uint32_t getARMBLTargetOpValue(const MCInst &MI, unsigned OpIdx,
149 uint32_t getARMBLXTargetOpValue(const MCInst &MI, unsigned OpIdx,
155 uint32_t getAdrLabelOpValue(const MCInst &MI, unsigned OpIdx,
158 uint32_t getThumbAdrLabelOpValue(const MCInst &MI, unsigned OpIdx,
161 uint32_t getT2AdrLabelOpValue(const MCInst &MI, unsigned OpIdx,
165 uint32_t getITMaskOpValue(const MCInst &MI, unsigned OpIdx,
171 uint32_t getMVEShiftImmOpValue(const MCInst &MI, unsigned OpIdx,
177 uint32_t getAddrModeImm12OpValue(const MCInst &MI, unsigned OpIdx,
182 uint32_t getThumbAddrModeRegRegOpValue(const MCInst &MI, unsigned OpIdx,
188 uint32_t getT2AddrModeImm8s4OpValue(const MCInst &MI, unsigned OpIdx,
194 uint32_t getT2AddrModeImm7s4OpValue(const MCInst &MI, unsigned OpIdx,
200 uint32_t getT2AddrModeImm0_1020s4OpValue(const MCInst &MI, unsigned OpIdx,
207 uint32_t getT2ScaledImmOpValue(const MCInst &MI, unsigned OpIdx,
213 uint32_t getMveAddrModeRQOpValue(const MCInst &MI, unsigned OpIdx,
220 uint32_t getMveAddrModeQOpValue(const MCInst &MI, unsigned OpIdx,
226 uint32_t getLdStSORegOpValue(const MCInst &MI, unsigned OpIdx,
231 uint32_t getLdStmModeOpValue(const MCInst &MI, unsigned OpIdx,
234 ARM_AM::AMSubMode Mode = (ARM_AM::AMSubMode)MI.getOperand(OpIdx).getImm();
260 uint32_t getAddrMode2OffsetOpValue(const MCInst &MI, unsigned OpIdx,
265 uint32_t getPostIdxRegOpValue(const MCInst &MI, unsigned OpIdx,
270 uint32_t getAddrMode3OffsetOpValue(const MCInst &MI, unsigned OpIdx,
275 uint32_t getAddrMode3OpValue(const MCInst &MI, unsigned OpIdx,
281 uint32_t getAddrModeThumbSPOpValue(const MCInst &MI, unsigned OpIdx,
286 uint32_t getAddrModeISOpValue(const MCInst &MI, unsigned OpIdx,
291 uint32_t getAddrModePCOpValue(const MCInst &MI, unsigned OpIdx,
296 uint32_t getAddrMode5OpValue(const MCInst &MI, unsigned OpIdx,
301 uint32_t getAddrMode5FP16OpValue(const MCInst &MI, unsigned OpIdx,
306 unsigned getCCOutOpValue(const MCInst &MI, unsigned Op,
311 return MI.getOperand(Op).getReg() == ARM::CPSR;
314 unsigned getModImmOpValue(const MCInst &MI, unsigned Op,
317 const MCOperand &MO = MI.getOperand(Op);
324 Fixups.push_back(MCFixup::create(0, Expr, Kind, MI.getLoc()));
333 unsigned getT2SOImmOpValue(const MCInst &MI, unsigned Op,
336 const MCOperand &MO = MI.getOperand(Op);
343 Fixups.push_back(MCFixup::create(0, Expr, Kind, MI.getLoc()));
352 unsigned getT2AddrModeSORegOpValue(const MCInst &MI, unsigned OpNum,
356 unsigned getT2AddrModeImmOpValue(const MCInst &MI, unsigned OpNum,
359 unsigned getT2AddrModeImm8OffsetOpValue(const MCInst &MI, unsigned OpNum,
364 unsigned getSORegRegOpValue(const MCInst &MI, unsigned Op,
367 unsigned getSORegImmOpValue(const MCInst &MI, unsigned Op,
370 unsigned getT2SORegOpValue(const MCInst &MI, unsigned Op,
374 unsigned getNEONVcvtImm32OpValue(const MCInst &MI, unsigned Op,
377 return 64 - MI.getOperand(Op).getImm();
380 unsigned getBitfieldInvertedMaskOpValue(const MCInst &MI, unsigned Op,
384 unsigned getRegisterListOpValue(const MCInst &MI, unsigned Op,
387 unsigned getAddrMode6AddressOpValue(const MCInst &MI, unsigned Op,
390 unsigned getAddrMode6OneLane32AddressOpValue(const MCInst &MI, unsigned Op,
393 unsigned getAddrMode6DupAddressOpValue(const MCInst &MI, unsigned Op,
396 unsigned getAddrMode6OffsetOpValue(const MCInst &MI, unsigned Op,
400 unsigned getShiftRight8Imm(const MCInst &MI, unsigned Op,
403 unsigned getShiftRight16Imm(const MCInst &MI, unsigned Op,
406 unsigned getShiftRight32Imm(const MCInst &MI, unsigned Op,
409 unsigned getShiftRight64Imm(const MCInst &MI, unsigned Op,
413 unsigned getThumbSRImmOpValue(const MCInst &MI, unsigned Op,
417 unsigned NEONThumb2DataIPostEncoder(const MCInst &MI,
420 unsigned NEONThumb2LoadStorePostEncoder(const MCInst &MI,
423 unsigned NEONThumb2DupPostEncoder(const MCInst &MI,
426 unsigned NEONThumb2V8PostEncoder(const MCInst &MI,
430 unsigned VFPThumb2PostEncoder(const MCInst &MI,
434 uint32_t getPowerTwoOpValue(const MCInst &MI, unsigned OpIdx,
438 void encodeInstruction(const MCInst &MI, SmallVectorImpl<char> &CB,
443 uint32_t getBFTargetOpValue(const MCInst &MI, unsigned OpIdx,
447 uint32_t getBFAfterTargetOpValue(const MCInst &MI, unsigned OpIdx,
451 uint32_t getVPTMaskOpValue(const MCInst &MI, unsigned OpIdx,
454 uint32_t getRestrictedCondCodeOpValue(const MCInst &MI, unsigned OpIdx,
458 uint32_t getMVEPairVectorIndexOpValue(const MCInst &MI, unsigned OpIdx,
468 unsigned ARMMCCodeEmitter::NEONThumb2DataIPostEncoder(const MCInst &MI,
488 unsigned ARMMCCodeEmitter::NEONThumb2LoadStorePostEncoder(const MCInst &MI,
502 unsigned ARMMCCodeEmitter::NEONThumb2DupPostEncoder(const MCInst &MI,
515 unsigned ARMMCCodeEmitter::NEONThumb2V8PostEncoder(const MCInst &MI,
528 VFPThumb2PostEncoder(const MCInst &MI, unsigned EncodedValue,
540 getMachineOpValue(const MCInst &MI, const MCOperand &MO,
579 EncodeAddrModeOpValues(const MCInst &MI, unsigned OpIdx, unsigned &Reg,
582 const MCOperand &MO = MI.getOperand(OpIdx);
583 const MCOperand &MO1 = MI.getOperand(OpIdx + 1);
608 static uint32_t getBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,
612 const MCOperand &MO = MI.getOperand(OpIdx);
619 Fixups.push_back(MCFixup::create(0, Expr, Kind, MI.getLoc()));
646 getThumbBLTargetOpValue(const MCInst &MI, unsigned OpIdx,
649 const MCOperand MO = MI.getOperand(OpIdx);
651 return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_thumb_bl,
659 getThumbBLXTargetOpValue(const MCInst &MI, unsigned OpIdx,
662 const MCOperand MO = MI.getOperand(OpIdx);
664 return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_thumb_blx,
671 getThumbBRTargetOpValue(const MCInst &MI, unsigned OpIdx,
674 const MCOperand MO = MI.getOperand(OpIdx);
676 return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_thumb_br,
683 getThumbBCCTargetOpValue(const MCInst &MI, unsigned OpIdx,
686 const MCOperand MO = MI.getOperand(OpIdx);
688 return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_thumb_bcc,
695 getThumbCBTargetOpValue(const MCInst &MI, unsigned OpIdx,
698 const MCOperand MO = MI.getOperand(OpIdx);
700 return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_thumb_cb, Fixups, STI);
705 static bool HasConditionalBranch(const MCInst &MI) {
706 int NumOp = MI.getNumOperands();
709 const MCOperand &MCOp1 = MI.getOperand(i);
710 const MCOperand &MCOp2 = MI.getOperand(i + 1);
724 getBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,
731 ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_t2_condbranch, Fixups, STI);
732 return getARMBranchTargetOpValue(MI, OpIdx, Fixups, STI);
738 getARMBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,
741 const MCOperand MO = MI.getOperand(OpIdx);
743 if (HasConditionalBranch(MI))
744 return ::getBranchTargetOpValue(MI, OpIdx,
746 return ::getBranchTargetOpValue(MI, OpIdx,
754 getARMBLTargetOpValue(const MCInst &MI, unsigned OpIdx,
757 const MCOperand MO = MI.getOperand(OpIdx);
759 if (HasConditionalBranch(MI))
760 return ::getBranchTargetOpValue(MI, OpIdx,
762 return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_uncondbl, Fixups, STI);
769 getARMBLXTargetOpValue(const MCInst &MI, unsigned OpIdx,
772 const MCOperand MO = MI.getOperand(OpIdx);
774 return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_blx, Fixups, STI);
782 const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups,
785 const MCOperand MO = MI.getOperand(OpIdx);
788 return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_t2_uncondbranch, Fixups, STI);
811 getAdrLabelOpValue(const MCInst &MI, unsigned OpIdx,
814 const MCOperand MO = MI.getOperand(OpIdx);
816 return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_adr_pcrel_12,
852 getT2AdrLabelOpValue(const MCInst &MI, unsigned OpIdx,
855 const MCOperand MO = MI.getOperand(OpIdx);
857 return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_t2_adr_pcrel_12,
872 getITMaskOpValue(const MCInst &MI, unsigned OpIdx,
875 const MCOperand MaskMO = MI.getOperand(OpIdx);
885 const MCOperand CondMO = MI.getOperand(OpIdx-1);
899 getThumbAdrLabelOpValue(const MCInst &MI, unsigned OpIdx,
902 const MCOperand MO = MI.getOperand(OpIdx);
904 return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_thumb_adr_pcrel_10,
912 getThumbAddrModeRegRegOpValue(const MCInst &MI, unsigned OpIdx,
918 const MCOperand &MO1 = MI.getOperand(OpIdx);
919 const MCOperand &MO2 = MI.getOperand(OpIdx + 1);
928 ARMMCCodeEmitter::getMVEShiftImmOpValue(const MCInst &MI, unsigned OpIdx,
940 switch(MI.getOpcode()) {
956 ShiftImm = MI.getOperand(OpIdx).getImm();
962 getAddrModeImm12OpValue(const MCInst &MI, unsigned OpIdx,
971 const MCOperand &MO = MI.getOperand(OpIdx);
973 const MCOperand &MO1 = MI.getOperand(OpIdx + 1);
975 isAdd = EncodeAddrModeOpValues(MI, OpIdx, Reg, Imm12, Fixups, STI);
982 Fixups.push_back(MCFixup::create(0, MO1.getExpr(), Kind, MI.getLoc()));
992 Fixups.push_back(MCFixup::create(0, MO.getExpr(), Kind, MI.getLoc()));
1017 getT2ScaledImmOpValue(const MCInst &MI, unsigned OpIdx,
1022 // the MI operands for the register and the offset into a single
1029 int32_t Imm = MI.getOperand(OpIdx).getImm();
1048 getMveAddrModeRQOpValue(const MCInst &MI, unsigned OpIdx,
1053 const MCOperand &M0 = MI.getOperand(OpIdx);
1054 const MCOperand &M1 = MI.getOperand(OpIdx + 1);
1068 getMveAddrModeQOpValue(const MCInst &MI, unsigned OpIdx,
1073 const MCOperand &M0 = MI.getOperand(OpIdx);
1074 const MCOperand &M1 = MI.getOperand(OpIdx + 1);
1099 getT2AddrModeImm8s4OpValue(const MCInst &MI, unsigned OpIdx,
1108 const MCOperand &MO = MI.getOperand(OpIdx);
1117 Fixups.push_back(MCFixup::create(0, Expr, Kind, MI.getLoc()));
1121 isAdd = EncodeAddrModeOpValues(MI, OpIdx, Reg, Imm8, Fixups, STI);
1125 // the MI operands for the register and the offset into a single
1141 ARMMCCodeEmitter::getT2AddrModeImm7s4OpValue(const MCInst &MI, unsigned OpIdx,
1149 bool isAdd = EncodeAddrModeOpValues(MI, OpIdx, Reg, Imm7, Fixups, STI);
1153 // the MI operands for the register and the offset into a single
1168 getT2AddrModeImm0_1020s4OpValue(const MCInst &MI, unsigned OpIdx,
1173 const MCOperand &MO = MI.getOperand(OpIdx);
1174 const MCOperand &MO1 = MI.getOperand(OpIdx + 1);
1180 uint32_t ARMMCCodeEmitter::getHiLoImmOpValue(const MCInst &MI, unsigned OpIdx,
1185 const MCOperand &MO = MI.getOperand(OpIdx);
1254 Fixups.push_back(MCFixup::create(0, E, Kind, MI.getLoc()));
1268 getLdStSORegOpValue(const MCInst &MI, unsigned OpIdx,
1271 const MCOperand &MO = MI.getOperand(OpIdx);
1272 const MCOperand &MO1 = MI.getOperand(OpIdx+1);
1273 const MCOperand &MO2 = MI.getOperand(OpIdx+2);
1302 getAddrMode2OffsetOpValue(const MCInst &MI, unsigned OpIdx,
1308 const MCOperand &MO = MI.getOperand(OpIdx);
1309 const MCOperand &MO1 = MI.getOperand(OpIdx+1);
1325 getPostIdxRegOpValue(const MCInst &MI, unsigned OpIdx,
1330 const MCOperand &MO = MI.getOperand(OpIdx);
1331 const MCOperand &MO1 = MI.getOperand(OpIdx+1);
1337 getAddrMode3OffsetOpValue(const MCInst &MI, unsigned OpIdx,
1344 const MCOperand &MO = MI.getOperand(OpIdx);
1345 const MCOperand &MO1 = MI.getOperand(OpIdx+1);
1357 getAddrMode3OpValue(const MCInst &MI, unsigned OpIdx,
1365 const MCOperand &MO = MI.getOperand(OpIdx);
1366 const MCOperand &MO1 = MI.getOperand(OpIdx+1);
1367 const MCOperand &MO2 = MI.getOperand(OpIdx+2);
1376 Fixups.push_back(MCFixup::create(0, Expr, Kind, MI.getLoc()));
1394 getAddrModeThumbSPOpValue(const MCInst &MI, unsigned OpIdx,
1399 const MCOperand &MO1 = MI.getOperand(OpIdx + 1);
1400 assert(MI.getOperand(OpIdx).getReg() == ARM::SP &&
1410 getAddrModeISOpValue(const MCInst &MI, unsigned OpIdx,
1416 const MCOperand &MO = MI.getOperand(OpIdx);
1417 const MCOperand &MO1 = MI.getOperand(OpIdx + 1);
1425 getAddrModePCOpValue(const MCInst &MI, unsigned OpIdx,
1428 const MCOperand MO = MI.getOperand(OpIdx);
1430 return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_thumb_cp, Fixups, STI);
1436 getAddrMode5OpValue(const MCInst &MI, unsigned OpIdx,
1445 const MCOperand &MO = MI.getOperand(OpIdx);
1458 Fixups.push_back(MCFixup::create(0, Expr, Kind, MI.getLoc()));
1462 EncodeAddrModeOpValues(MI, OpIdx, Reg, Imm8, Fixups, STI);
1476 getAddrMode5FP16OpValue(const MCInst &MI, unsigned OpIdx,
1485 const MCOperand &MO = MI.getOperand(OpIdx);
1498 Fixups.push_back(MCFixup::create(0, Expr, Kind, MI.getLoc()));
1502 EncodeAddrModeOpValues(MI, OpIdx, Reg, Imm8, Fixups, STI);
1515 getSORegRegOpValue(const MCInst &MI, unsigned OpIdx,
1528 const MCOperand &MO = MI.getOperand(OpIdx);
1529 const MCOperand &MO1 = MI.getOperand(OpIdx + 1);
1530 const MCOperand &MO2 = MI.getOperand(OpIdx + 2);
1563 getSORegImmOpValue(const MCInst &MI, unsigned OpIdx,
1574 const MCOperand &MO = MI.getOperand(OpIdx);
1575 const MCOperand &MO1 = MI.getOperand(OpIdx + 1);
1610 getT2AddrModeSORegOpValue(const MCInst &MI, unsigned OpNum,
1613 const MCOperand &MO1 = MI.getOperand(OpNum);
1614 const MCOperand &MO2 = MI.getOperand(OpNum+1);
1615 const MCOperand &MO3 = MI.getOperand(OpNum+2);
1630 getT2AddrModeImmOpValue(const MCInst &MI, unsigned OpNum,
1633 const MCOperand &MO1 = MI.getOperand(OpNum);
1634 const MCOperand &MO2 = MI.getOperand(OpNum+1);
1655 getT2AddrModeImm8OffsetOpValue(const MCInst &MI, unsigned OpNum,
1658 const MCOperand &MO1 = MI.getOperand(OpNum);
1672 getT2SORegOpValue(const MCInst &MI, unsigned OpIdx,
1683 const MCOperand &MO = MI.getOperand(OpIdx);
1684 const MCOperand &MO1 = MI.getOperand(OpIdx + 1);
1715 getBitfieldInvertedMaskOpValue(const MCInst &MI, unsigned Op,
1720 const MCOperand &MO = MI.getOperand(Op);
1729 getRegisterListOpValue(const MCInst &MI, unsigned Op,
1738 MCRegister Reg = MI.getOperand(Op).getReg();
1747 unsigned NumRegs = (MI.getNumOperands() - Op) & 0xff;
1750 if (MI.getOpcode() == ARM::VSCCLRMD)
1753 else if (MI.getOpcode() == ARM::VSCCLRMS) {
1758 for (unsigned I = Op, E = MI.getNumOperands(); I < E; ++I) {
1759 Reg = MI.getOperand(I).getReg();
1772 assert(is_sorted(drop_begin(MI, Op),
1777 for (unsigned I = Op, E = MI.getNumOperands(); I < E; ++I) {
1778 unsigned RegNo = MRI.getEncodingValue(MI.getOperand(I).getReg());
1789 getAddrMode6AddressOpValue(const MCInst &MI, unsigned Op,
1792 const MCOperand &Reg = MI.getOperand(Op);
1793 const MCOperand &Imm = MI.getOperand(Op + 1);
1813 getAddrMode6OneLane32AddressOpValue(const MCInst &MI, unsigned Op,
1816 const MCOperand &Reg = MI.getOperand(Op);
1817 const MCOperand &Imm = MI.getOperand(Op + 1);
1840 getAddrMode6DupAddressOpValue(const MCInst &MI, unsigned Op,
1843 const MCOperand &Reg = MI.getOperand(Op);
1844 const MCOperand &Imm = MI.getOperand(Op + 1);
1861 getAddrMode6OffsetOpValue(const MCInst &MI, unsigned Op,
1864 const MCOperand &MO = MI.getOperand(Op);
1871 getShiftRight8Imm(const MCInst &MI, unsigned Op,
1874 return 8 - MI.getOperand(Op).getImm();
1878 getShiftRight16Imm(const MCInst &MI, unsigned Op,
1881 return 16 - MI.getOperand(Op).getImm();
1885 getShiftRight32Imm(const MCInst &MI, unsigned Op,
1888 return 32 - MI.getOperand(Op).getImm();
1892 getShiftRight64Imm(const MCInst &MI, unsigned Op,
1895 return 64 - MI.getOperand(Op).getImm();
1898 void ARMMCCodeEmitter::encodeInstruction(const MCInst &MI,
1903 const MCInstrDesc &Desc = MCII.get(MI.getOpcode());
1916 uint32_t Binary = getBinaryCodeForInstr(MI, Fixups, STI);
1932 ARMMCCodeEmitter::getBFTargetOpValue(const MCInst &MI, unsigned OpIdx,
1935 const MCOperand MO = MI.getOperand(OpIdx);
1937 return ::getBranchTargetOpValue(MI, OpIdx, fixup, Fixups, STI);
1942 ARMMCCodeEmitter::getBFAfterTargetOpValue(const MCInst &MI, unsigned OpIdx,
1945 const MCOperand MO = MI.getOperand(OpIdx);
1946 const MCOperand BranchMO = MI.getOperand(0);
1953 Fixups.push_back(llvm::MCFixup::create(0, DiffExpr, Kind, MI.getLoc()));
1964 uint32_t ARMMCCodeEmitter::getVPTMaskOpValue(const MCInst &MI, unsigned OpIdx,
1967 const MCOperand MO = MI.getOperand(OpIdx);
1996 const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups,
1999 const MCOperand MO = MI.getOperand(OpIdx);
2024 getPowerTwoOpValue(const MCInst &MI, unsigned OpIdx,
2027 const MCOperand &MO = MI.getOperand(OpIdx);
2034 getMVEPairVectorIndexOpValue(const MCInst &MI, unsigned OpIdx,
2037 const MCOperand MO = MI.getOperand(OpIdx);