Lines Matching +full:0 +full:x2c54
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
37 auto *MDN = dyn_cast<MDTuple>(NamedMD->getOperand(0));
39 if (auto *MDS = dyn_cast<MDString>(MDN->getOperand(0)))
55 auto *Tuple = dyn_cast<MDTuple>(NamedMD->getOperand(0));
58 for (unsigned I = 0, E = Tuple->getNumOperands() & -2; I != E; I += 2) {
80 for (unsigned I = 0; I != Blob.size() / sizeof(uint32_t) / 2; ++I)
169 // Get a register from the metadata, or 0 if not currently set.
174 return 0;
177 return 0;
185 // In the new MsgPack format, ignore register numbered >= 0x10000000. It
187 if (Reg >= 0x10000000)
201 // In the new MsgPack format, ignore register numbered >= 0x10000000. It
203 if (Reg >= 0x10000000)
222 // Default to uint64_t 0 so additional calls to setRegister will allow
224 N = (uint64_t)0;
423 {0x2c07, "SPI_SHADER_PGM_RSRC3_PS"},
424 {0x2c46, "SPI_SHADER_PGM_RSRC3_VS"},
425 {0x2c87, "SPI_SHADER_PGM_RSRC3_GS"},
426 {0x2cc7, "SPI_SHADER_PGM_RSRC3_ES"},
427 {0x2d07, "SPI_SHADER_PGM_RSRC3_HS"},
428 {0x2d47, "SPI_SHADER_PGM_RSRC3_LS"},
430 {0xa1c3, "SPI_SHADER_POS_FORMAT"},
431 {0xa1b1, "SPI_VS_OUT_CONFIG"},
432 {0xa207, "PA_CL_VS_OUT_CNTL"},
433 {0xa204, "PA_CL_CLIP_CNTL"},
434 {0xa206, "PA_CL_VTE_CNTL"},
435 {0xa2f9, "PA_SU_VTX_CNTL"},
436 {0xa293, "PA_SC_MODE_CNTL_1"},
437 {0xa2a1, "VGT_PRIMITIVEID_EN"},
438 {0x2c81, "SPI_SHADER_PGM_RSRC4_GS"},
439 {0x2e18, "COMPUTE_TMPRING_SIZE"},
440 {0xa1b5, "SPI_INTERP_CONTROL_0"},
441 {0xa1ba, "SPI_TMPRING_SIZE"},
442 {0xa1c4, "SPI_SHADER_Z_FORMAT"},
443 {0xa1c5, "SPI_SHADER_COL_FORMAT"},
444 {0xa203, "DB_SHADER_CONTROL"},
445 {0xa08f, "CB_SHADER_MASK"},
446 {0xa191, "SPI_PS_INPUT_CNTL_0"},
447 {0xa192, "SPI_PS_INPUT_CNTL_1"},
448 {0xa193, "SPI_PS_INPUT_CNTL_2"},
449 {0xa194, "SPI_PS_INPUT_CNTL_3"},
450 {0xa195, "SPI_PS_INPUT_CNTL_4"},
451 {0xa196, "SPI_PS_INPUT_CNTL_5"},
452 {0xa197, "SPI_PS_INPUT_CNTL_6"},
453 {0xa198, "SPI_PS_INPUT_CNTL_7"},
454 {0xa199, "SPI_PS_INPUT_CNTL_8"},
455 {0xa19a, "SPI_PS_INPUT_CNTL_9"},
456 {0xa19b, "SPI_PS_INPUT_CNTL_10"},
457 {0xa19c, "SPI_PS_INPUT_CNTL_11"},
458 {0xa19d, "SPI_PS_INPUT_CNTL_12"},
459 {0xa19e, "SPI_PS_INPUT_CNTL_13"},
460 {0xa19f, "SPI_PS_INPUT_CNTL_14"},
461 {0xa1a0, "SPI_PS_INPUT_CNTL_15"},
462 {0xa1a1, "SPI_PS_INPUT_CNTL_16"},
463 {0xa1a2, "SPI_PS_INPUT_CNTL_17"},
464 {0xa1a3, "SPI_PS_INPUT_CNTL_18"},
465 {0xa1a4, "SPI_PS_INPUT_CNTL_19"},
466 {0xa1a5, "SPI_PS_INPUT_CNTL_20"},
467 {0xa1a6, "SPI_PS_INPUT_CNTL_21"},
468 {0xa1a7, "SPI_PS_INPUT_CNTL_22"},
469 {0xa1a8, "SPI_PS_INPUT_CNTL_23"},
470 {0xa1a9, "SPI_PS_INPUT_CNTL_24"},
471 {0xa1aa, "SPI_PS_INPUT_CNTL_25"},
472 {0xa1ab, "SPI_PS_INPUT_CNTL_26"},
473 {0xa1ac, "SPI_PS_INPUT_CNTL_27"},
474 {0xa1ad, "SPI_PS_INPUT_CNTL_28"},
475 {0xa1ae, "SPI_PS_INPUT_CNTL_29"},
476 {0xa1af, "SPI_PS_INPUT_CNTL_30"},
477 {0xa1b0, "SPI_PS_INPUT_CNTL_31"},
479 {0xa2ce, "VGT_GS_MAX_VERT_OUT"},
480 {0xa2ab, "VGT_ESGS_RING_ITEMSIZE"},
481 {0xa290, "VGT_GS_MODE"},
482 {0xa291, "VGT_GS_ONCHIP_CNTL"},
483 {0xa2d7, "VGT_GS_VERT_ITEMSIZE"},
484 {0xa2d8, "VGT_GS_VERT_ITEMSIZE_1"},
485 {0xa2d9, "VGT_GS_VERT_ITEMSIZE_2"},
486 {0xa2da, "VGT_GS_VERT_ITEMSIZE_3"},
487 {0xa298, "VGT_GSVS_RING_OFFSET_1"},
488 {0xa299, "VGT_GSVS_RING_OFFSET_2"},
489 {0xa29a, "VGT_GSVS_RING_OFFSET_3"},
491 {0xa2e4, "VGT_GS_INSTANCE_CNT"},
492 {0xa297, "VGT_GS_PER_VS"},
493 {0xa29b, "VGT_GS_OUT_PRIM_TYPE"},
494 {0xa2ac, "VGT_GSVS_RING_ITEMSIZE"},
496 {0xa2ad, "VGT_REUSE_OFF"},
497 {0xa1b8, "SPI_BARYC_CNTL"},
499 {0x2c4c, "SPI_SHADER_USER_DATA_VS_0"},
500 {0x2c4d, "SPI_SHADER_USER_DATA_VS_1"},
501 {0x2c4e, "SPI_SHADER_USER_DATA_VS_2"},
502 {0x2c4f, "SPI_SHADER_USER_DATA_VS_3"},
503 {0x2c50, "SPI_SHADER_USER_DATA_VS_4"},
504 {0x2c51, "SPI_SHADER_USER_DATA_VS_5"},
505 {0x2c52, "SPI_SHADER_USER_DATA_VS_6"},
506 {0x2c53, "SPI_SHADER_USER_DATA_VS_7"},
507 {0x2c54, "SPI_SHADER_USER_DATA_VS_8"},
508 {0x2c55, "SPI_SHADER_USER_DATA_VS_9"},
509 {0x2c56, "SPI_SHADER_USER_DATA_VS_10"},
510 {0x2c57, "SPI_SHADER_USER_DATA_VS_11"},
511 {0x2c58, "SPI_SHADER_USER_DATA_VS_12"},
512 {0x2c59, "SPI_SHADER_USER_DATA_VS_13"},
513 {0x2c5a, "SPI_SHADER_USER_DATA_VS_14"},
514 {0x2c5b, "SPI_SHADER_USER_DATA_VS_15"},
515 {0x2c5c, "SPI_SHADER_USER_DATA_VS_16"},
516 {0x2c5d, "SPI_SHADER_USER_DATA_VS_17"},
517 {0x2c5e, "SPI_SHADER_USER_DATA_VS_18"},
518 {0x2c5f, "SPI_SHADER_USER_DATA_VS_19"},
519 {0x2c60, "SPI_SHADER_USER_DATA_VS_20"},
520 {0x2c61, "SPI_SHADER_USER_DATA_VS_21"},
521 {0x2c62, "SPI_SHADER_USER_DATA_VS_22"},
522 {0x2c63, "SPI_SHADER_USER_DATA_VS_23"},
523 {0x2c64, "SPI_SHADER_USER_DATA_VS_24"},
524 {0x2c65, "SPI_SHADER_USER_DATA_VS_25"},
525 {0x2c66, "SPI_SHADER_USER_DATA_VS_26"},
526 {0x2c67, "SPI_SHADER_USER_DATA_VS_27"},
527 {0x2c68, "SPI_SHADER_USER_DATA_VS_28"},
528 {0x2c69, "SPI_SHADER_USER_DATA_VS_29"},
529 {0x2c6a, "SPI_SHADER_USER_DATA_VS_30"},
530 {0x2c6b, "SPI_SHADER_USER_DATA_VS_31"},
532 {0x2c8c, "SPI_SHADER_USER_DATA_GS_0"},
533 {0x2c8d, "SPI_SHADER_USER_DATA_GS_1"},
534 {0x2c8e, "SPI_SHADER_USER_DATA_GS_2"},
535 {0x2c8f, "SPI_SHADER_USER_DATA_GS_3"},
536 {0x2c90, "SPI_SHADER_USER_DATA_GS_4"},
537 {0x2c91, "SPI_SHADER_USER_DATA_GS_5"},
538 {0x2c92, "SPI_SHADER_USER_DATA_GS_6"},
539 {0x2c93, "SPI_SHADER_USER_DATA_GS_7"},
540 {0x2c94, "SPI_SHADER_USER_DATA_GS_8"},
541 {0x2c95, "SPI_SHADER_USER_DATA_GS_9"},
542 {0x2c96, "SPI_SHADER_USER_DATA_GS_10"},
543 {0x2c97, "SPI_SHADER_USER_DATA_GS_11"},
544 {0x2c98, "SPI_SHADER_USER_DATA_GS_12"},
545 {0x2c99, "SPI_SHADER_USER_DATA_GS_13"},
546 {0x2c9a, "SPI_SHADER_USER_DATA_GS_14"},
547 {0x2c9b, "SPI_SHADER_USER_DATA_GS_15"},
548 {0x2c9c, "SPI_SHADER_USER_DATA_GS_16"},
549 {0x2c9d, "SPI_SHADER_USER_DATA_GS_17"},
550 {0x2c9e, "SPI_SHADER_USER_DATA_GS_18"},
551 {0x2c9f, "SPI_SHADER_USER_DATA_GS_19"},
552 {0x2ca0, "SPI_SHADER_USER_DATA_GS_20"},
553 {0x2ca1, "SPI_SHADER_USER_DATA_GS_21"},
554 {0x2ca2, "SPI_SHADER_USER_DATA_GS_22"},
555 {0x2ca3, "SPI_SHADER_USER_DATA_GS_23"},
556 {0x2ca4, "SPI_SHADER_USER_DATA_GS_24"},
557 {0x2ca5, "SPI_SHADER_USER_DATA_GS_25"},
558 {0x2ca6, "SPI_SHADER_USER_DATA_GS_26"},
559 {0x2ca7, "SPI_SHADER_USER_DATA_GS_27"},
560 {0x2ca8, "SPI_SHADER_USER_DATA_GS_28"},
561 {0x2ca9, "SPI_SHADER_USER_DATA_GS_29"},
562 {0x2caa, "SPI_SHADER_USER_DATA_GS_30"},
563 {0x2cab, "SPI_SHADER_USER_DATA_GS_31"},
565 {0x2ccc, "SPI_SHADER_USER_DATA_ES_0"},
566 {0x2ccd, "SPI_SHADER_USER_DATA_ES_1"},
567 {0x2cce, "SPI_SHADER_USER_DATA_ES_2"},
568 {0x2ccf, "SPI_SHADER_USER_DATA_ES_3"},
569 {0x2cd0, "SPI_SHADER_USER_DATA_ES_4"},
570 {0x2cd1, "SPI_SHADER_USER_DATA_ES_5"},
571 {0x2cd2, "SPI_SHADER_USER_DATA_ES_6"},
572 {0x2cd3, "SPI_SHADER_USER_DATA_ES_7"},
573 {0x2cd4, "SPI_SHADER_USER_DATA_ES_8"},
574 {0x2cd5, "SPI_SHADER_USER_DATA_ES_9"},
575 {0x2cd6, "SPI_SHADER_USER_DATA_ES_10"},
576 {0x2cd7, "SPI_SHADER_USER_DATA_ES_11"},
577 {0x2cd8, "SPI_SHADER_USER_DATA_ES_12"},
578 {0x2cd9, "SPI_SHADER_USER_DATA_ES_13"},
579 {0x2cda, "SPI_SHADER_USER_DATA_ES_14"},
580 {0x2cdb, "SPI_SHADER_USER_DATA_ES_15"},
581 {0x2cdc, "SPI_SHADER_USER_DATA_ES_16"},
582 {0x2cdd, "SPI_SHADER_USER_DATA_ES_17"},
583 {0x2cde, "SPI_SHADER_USER_DATA_ES_18"},
584 {0x2cdf, "SPI_SHADER_USER_DATA_ES_19"},
585 {0x2ce0, "SPI_SHADER_USER_DATA_ES_20"},
586 {0x2ce1, "SPI_SHADER_USER_DATA_ES_21"},
587 {0x2ce2, "SPI_SHADER_USER_DATA_ES_22"},
588 {0x2ce3, "SPI_SHADER_USER_DATA_ES_23"},
589 {0x2ce4, "SPI_SHADER_USER_DATA_ES_24"},
590 {0x2ce5, "SPI_SHADER_USER_DATA_ES_25"},
591 {0x2ce6, "SPI_SHADER_USER_DATA_ES_26"},
592 {0x2ce7, "SPI_SHADER_USER_DATA_ES_27"},
593 {0x2ce8, "SPI_SHADER_USER_DATA_ES_28"},
594 {0x2ce9, "SPI_SHADER_USER_DATA_ES_29"},
595 {0x2cea, "SPI_SHADER_USER_DATA_ES_30"},
596 {0x2ceb, "SPI_SHADER_USER_DATA_ES_31"},
598 {0x2c0c, "SPI_SHADER_USER_DATA_PS_0"},
599 {0x2c0d, "SPI_SHADER_USER_DATA_PS_1"},
600 {0x2c0e, "SPI_SHADER_USER_DATA_PS_2"},
601 {0x2c0f, "SPI_SHADER_USER_DATA_PS_3"},
602 {0x2c10, "SPI_SHADER_USER_DATA_PS_4"},
603 {0x2c11, "SPI_SHADER_USER_DATA_PS_5"},
604 {0x2c12, "SPI_SHADER_USER_DATA_PS_6"},
605 {0x2c13, "SPI_SHADER_USER_DATA_PS_7"},
606 {0x2c14, "SPI_SHADER_USER_DATA_PS_8"},
607 {0x2c15, "SPI_SHADER_USER_DATA_PS_9"},
608 {0x2c16, "SPI_SHADER_USER_DATA_PS_10"},
609 {0x2c17, "SPI_SHADER_USER_DATA_PS_11"},
610 {0x2c18, "SPI_SHADER_USER_DATA_PS_12"},
611 {0x2c19, "SPI_SHADER_USER_DATA_PS_13"},
612 {0x2c1a, "SPI_SHADER_USER_DATA_PS_14"},
613 {0x2c1b, "SPI_SHADER_USER_DATA_PS_15"},
614 {0x2c1c, "SPI_SHADER_USER_DATA_PS_16"},
615 {0x2c1d, "SPI_SHADER_USER_DATA_PS_17"},
616 {0x2c1e, "SPI_SHADER_USER_DATA_PS_18"},
617 {0x2c1f, "SPI_SHADER_USER_DATA_PS_19"},
618 {0x2c20, "SPI_SHADER_USER_DATA_PS_20"},
619 {0x2c21, "SPI_SHADER_USER_DATA_PS_21"},
620 {0x2c22, "SPI_SHADER_USER_DATA_PS_22"},
621 {0x2c23, "SPI_SHADER_USER_DATA_PS_23"},
622 {0x2c24, "SPI_SHADER_USER_DATA_PS_24"},
623 {0x2c25, "SPI_SHADER_USER_DATA_PS_25"},
624 {0x2c26, "SPI_SHADER_USER_DATA_PS_26"},
625 {0x2c27, "SPI_SHADER_USER_DATA_PS_27"},
626 {0x2c28, "SPI_SHADER_USER_DATA_PS_28"},
627 {0x2c29, "SPI_SHADER_USER_DATA_PS_29"},
628 {0x2c2a, "SPI_SHADER_USER_DATA_PS_30"},
629 {0x2c2b, "SPI_SHADER_USER_DATA_PS_31"},
631 {0x2e40, "COMPUTE_USER_DATA_0"},
632 {0x2e41, "COMPUTE_USER_DATA_1"},
633 {0x2e42, "COMPUTE_USER_DATA_2"},
634 {0x2e43, "COMPUTE_USER_DATA_3"},
635 {0x2e44, "COMPUTE_USER_DATA_4"},
636 {0x2e45, "COMPUTE_USER_DATA_5"},
637 {0x2e46, "COMPUTE_USER_DATA_6"},
638 {0x2e47, "COMPUTE_USER_DATA_7"},
639 {0x2e48, "COMPUTE_USER_DATA_8"},
640 {0x2e49, "COMPUTE_USER_DATA_9"},
641 {0x2e4a, "COMPUTE_USER_DATA_10"},
642 {0x2e4b, "COMPUTE_USER_DATA_11"},
643 {0x2e4c, "COMPUTE_USER_DATA_12"},
644 {0x2e4d, "COMPUTE_USER_DATA_13"},
645 {0x2e4e, "COMPUTE_USER_DATA_14"},
646 {0x2e4f, "COMPUTE_USER_DATA_15"},
648 {0x2e07, "COMPUTE_NUM_THREAD_X"},
649 {0x2e08, "COMPUTE_NUM_THREAD_Y"},
650 {0x2e09, "COMPUTE_NUM_THREAD_Z"},
651 {0xa2db, "VGT_TF_PARAM"},
652 {0xa2d6, "VGT_LS_HS_CONFIG"},
653 {0xa287, "VGT_HOS_MIN_TESS_LEVEL"},
654 {0xa286, "VGT_HOS_MAX_TESS_LEVEL"},
655 {0xa2f8, "PA_SC_AA_CONFIG"},
656 {0xa310, "PA_SC_SHADER_CONTROL"},
657 {0xa313, "PA_SC_CONSERVATIVE_RASTERIZATION_CNTL"},
659 {0x2d0c, "SPI_SHADER_USER_DATA_HS_0"},
660 {0x2d0d, "SPI_SHADER_USER_DATA_HS_1"},
661 {0x2d0e, "SPI_SHADER_USER_DATA_HS_2"},
662 {0x2d0f, "SPI_SHADER_USER_DATA_HS_3"},
663 {0x2d10, "SPI_SHADER_USER_DATA_HS_4"},
664 {0x2d11, "SPI_SHADER_USER_DATA_HS_5"},
665 {0x2d12, "SPI_SHADER_USER_DATA_HS_6"},
666 {0x2d13, "SPI_SHADER_USER_DATA_HS_7"},
667 {0x2d14, "SPI_SHADER_USER_DATA_HS_8"},
668 {0x2d15, "SPI_SHADER_USER_DATA_HS_9"},
669 {0x2d16, "SPI_SHADER_USER_DATA_HS_10"},
670 {0x2d17, "SPI_SHADER_USER_DATA_HS_11"},
671 {0x2d18, "SPI_SHADER_USER_DATA_HS_12"},
672 {0x2d19, "SPI_SHADER_USER_DATA_HS_13"},
673 {0x2d1a, "SPI_SHADER_USER_DATA_HS_14"},
674 {0x2d1b, "SPI_SHADER_USER_DATA_HS_15"},
675 {0x2d1c, "SPI_SHADER_USER_DATA_HS_16"},
676 {0x2d1d, "SPI_SHADER_USER_DATA_HS_17"},
677 {0x2d1e, "SPI_SHADER_USER_DATA_HS_18"},
678 {0x2d1f, "SPI_SHADER_USER_DATA_HS_19"},
679 {0x2d20, "SPI_SHADER_USER_DATA_HS_20"},
680 {0x2d21, "SPI_SHADER_USER_DATA_HS_21"},
681 {0x2d22, "SPI_SHADER_USER_DATA_HS_22"},
682 {0x2d23, "SPI_SHADER_USER_DATA_HS_23"},
683 {0x2d24, "SPI_SHADER_USER_DATA_HS_24"},
684 {0x2d25, "SPI_SHADER_USER_DATA_HS_25"},
685 {0x2d26, "SPI_SHADER_USER_DATA_HS_26"},
686 {0x2d27, "SPI_SHADER_USER_DATA_HS_27"},
687 {0x2d28, "SPI_SHADER_USER_DATA_HS_28"},
688 {0x2d29, "SPI_SHADER_USER_DATA_HS_29"},
689 {0x2d2a, "SPI_SHADER_USER_DATA_HS_30"},
690 {0x2d2b, "SPI_SHADER_USER_DATA_HS_31"},
692 {0x2d4c, "SPI_SHADER_USER_DATA_LS_0"},
693 {0x2d4d, "SPI_SHADER_USER_DATA_LS_1"},
694 {0x2d4e, "SPI_SHADER_USER_DATA_LS_2"},
695 {0x2d4f, "SPI_SHADER_USER_DATA_LS_3"},
696 {0x2d50, "SPI_SHADER_USER_DATA_LS_4"},
697 {0x2d51, "SPI_SHADER_USER_DATA_LS_5"},
698 {0x2d52, "SPI_SHADER_USER_DATA_LS_6"},
699 {0x2d53, "SPI_SHADER_USER_DATA_LS_7"},
700 {0x2d54, "SPI_SHADER_USER_DATA_LS_8"},
701 {0x2d55, "SPI_SHADER_USER_DATA_LS_9"},
702 {0x2d56, "SPI_SHADER_USER_DATA_LS_10"},
703 {0x2d57, "SPI_SHADER_USER_DATA_LS_11"},
704 {0x2d58, "SPI_SHADER_USER_DATA_LS_12"},
705 {0x2d59, "SPI_SHADER_USER_DATA_LS_13"},
706 {0x2d5a, "SPI_SHADER_USER_DATA_LS_14"},
707 {0x2d5b, "SPI_SHADER_USER_DATA_LS_15"},
709 {0xa2aa, "IA_MULTI_VGT_PARAM"},
710 {0xa2a5, "VGT_GS_MAX_PRIMS_PER_SUBGROUP"},
711 {0xa2e6, "VGT_STRMOUT_BUFFER_CONFIG"},
712 {0xa2e5, "VGT_STRMOUT_CONFIG"},
713 {0xa2b5, "VGT_STRMOUT_VTX_STRIDE_0"},
714 {0xa2b9, "VGT_STRMOUT_VTX_STRIDE_1"},
715 {0xa2bd, "VGT_STRMOUT_VTX_STRIDE_2"},
716 {0xa2c1, "VGT_STRMOUT_VTX_STRIDE_3"},
717 {0xa316, "VGT_VERTEX_REUSE_BLOCK_CNTL"},
719 {0x2e28, "COMPUTE_PGM_RSRC3"},
720 {0x2e2a, "COMPUTE_SHADER_CHKSUM"},
721 {0x2e24, "COMPUTE_USER_ACCUM_0"},
722 {0x2e25, "COMPUTE_USER_ACCUM_1"},
723 {0x2e26, "COMPUTE_USER_ACCUM_2"},
724 {0x2e27, "COMPUTE_USER_ACCUM_3"},
725 {0xa1ff, "GE_MAX_OUTPUT_PER_SUBGROUP"},
726 {0xa2d3, "GE_NGG_SUBGRP_CNTL"},
727 {0xc25f, "GE_STEREO_CNTL"},
728 {0xc262, "GE_USER_VGPR_EN"},
729 {0xc258, "IA_MULTI_VGT_PARAM_PIPED"},
730 {0xa210, "PA_STEREO_CNTL"},
731 {0xa1c2, "SPI_SHADER_IDX_FORMAT"},
732 {0x2c80, "SPI_SHADER_PGM_CHKSUM_GS"},
733 {0x2d00, "SPI_SHADER_PGM_CHKSUM_HS"},
734 {0x2c06, "SPI_SHADER_PGM_CHKSUM_PS"},
735 {0x2c45, "SPI_SHADER_PGM_CHKSUM_VS"},
736 {0x2c88, "SPI_SHADER_PGM_LO_GS"},
737 {0x2cb2, "SPI_SHADER_USER_ACCUM_ESGS_0"},
738 {0x2cb3, "SPI_SHADER_USER_ACCUM_ESGS_1"},
739 {0x2cb4, "SPI_SHADER_USER_ACCUM_ESGS_2"},
740 {0x2cb5, "SPI_SHADER_USER_ACCUM_ESGS_3"},
741 {0x2d32, "SPI_SHADER_USER_ACCUM_LSHS_0"},
742 {0x2d33, "SPI_SHADER_USER_ACCUM_LSHS_1"},
743 {0x2d34, "SPI_SHADER_USER_ACCUM_LSHS_2"},
744 {0x2d35, "SPI_SHADER_USER_ACCUM_LSHS_3"},
745 {0x2c32, "SPI_SHADER_USER_ACCUM_PS_0"},
746 {0x2c33, "SPI_SHADER_USER_ACCUM_PS_1"},
747 {0x2c34, "SPI_SHADER_USER_ACCUM_PS_2"},
748 {0x2c35, "SPI_SHADER_USER_ACCUM_PS_3"},
749 {0x2c72, "SPI_SHADER_USER_ACCUM_VS_0"},
750 {0x2c73, "SPI_SHADER_USER_ACCUM_VS_1"},
751 {0x2c74, "SPI_SHADER_USER_ACCUM_VS_2"},
752 {0x2c75, "SPI_SHADER_USER_ACCUM_VS_3"},
754 {0, nullptr}};
779 Stream << "0x" << Twine::utohexstr(Reg) << ",0x" << Twine::utohexstr(Val);
847 // In the registers map, some keys may be of the form "0xa191
860 if (S.consumeInteger(0, Val)) {
877 .getArray(/*Convert=*/true)[0]
895 .getArray(/*Convert=*/true)[0]
918 .getArray(/*Convert=*/true)[0]
934 .getArray(/*Convert=*/true)[0]
972 .getArray(/*Convert=*/true)[0]
994 // 0 (no PAL metadata).
1025 "illegal index to PAL version - should be 0 (major) or 1 (minor)");
1041 unsigned AMDGPUPALMetadata::getPALMajorVersion() { return getPALVersion(0); }