Lines Matching defs:Src1
2707 MachineOperand &Src1,
2831 MachineOperand &Src1 = MI.getOperand(Src1Idx);
2832 if (!isLegalToSwap(MI, Src0Idx, &Src0, Src1Idx, &Src1)) {
2836 if (Src0.isReg() && Src1.isReg()) {
2840 } else if (Src0.isReg() && !Src1.isReg()) {
2841 CommutedMI = swapRegAndNonRegOperand(MI, Src0, Src1);
2842 } else if (!Src0.isReg() && Src1.isReg()) {
2843 CommutedMI = swapRegAndNonRegOperand(MI, Src1, Src0);
2844 } else if (Src0.isImm() && Src1.isImm()) {
2845 CommutedMI = swapImmOperands(MI, Src0, Src1);
2853 Src1, AMDGPU::OpName::src1_modifiers);
2855 swapSourceModifiers(MI, Src0, AMDGPU::OpName::src0_sel, Src1,
3568 MachineOperand *Src1 = getNamedOperand(UseMI, AMDGPU::OpName::src1);
3573 (Src1->isReg() && Src1->getReg() == Reg)) {
3575 Src1->isReg() && Src1->getReg() == Reg ? Src0 : Src1;
3612 const int64_t Imm = getImmFor(RegSrc == Src1 ? *Src0 : *Src1);
3629 Src1->ChangeToImmediate(Imm);
3664 if (Src1->isReg() && !Src0Inlined) {
3666 MachineInstr *Def = MRI->getUniqueVRegDef(Src1->getReg());
3669 MRI->hasOneUse(Src1->getReg()) && commuteInstruction(UseMI))
3671 else if (RI.isSGPRReg(*MRI, Src1->getReg()))
3673 // VGPR is okay as Src1 - fallthrough
4008 const MachineOperand *Src1 = getNamedOperand(MI, AMDGPU::OpName::src1);
4069 .add(*Src1)
4084 if (!Src0Literal && getFoldableImm(Src1, Imm, &DefMI)) {
4108 Src1)) {
4111 .add(*Src1)
4141 .add(*Src1)
4518 const MachineOperand *Src1
4520 if (!Src1->isReg() || !RI.isVGPR(MRI, Src1->getReg()))
4543 const MachineOperand *Src1 = getNamedOperand(MI, AMDGPU::OpName::src1);
4544 if (Src1 && (!Src1->isReg() || !RI.isVGPR(MRI, Src1->getReg()) ||
5128 const MachineOperand &Src1 = MI.getOperand(Src1Idx);
5130 if (Src0.isReg() && Src1.isReg() && Src2.isReg()) {
5131 if (!compareMachineOp(Src0, Src1) &&
5150 const MachineOperand &Src1 = MI.getOperand(Src1Idx);
5152 if (!isRegOrFI(Src0) && !isRegOrFI(Src1) &&
5154 !isInlineConstant(Src1, Desc.operands()[Src1Idx]) &&
5155 !Src0.isIdenticalTo(Src1)) {
6031 MachineOperand &Src1 = MI.getOperand(Src1Idx);
6051 if (Src1.isReg() && RI.isVGPR(MRI, Src1.getReg())) {
6055 .add(Src1);
6056 Src1.ChangeToRegister(Reg, false);
6065 if (Src1.isReg() && RI.isAGPR(MRI, Src1.getReg()))
6077 if (isLegalRegOperand(MRI, InstrDesc.operands()[Src1Idx], Src1))
6083 if (Opc == AMDGPU::V_READLANE_B32 && Src1.isReg() &&
6084 RI.isVGPR(MRI, Src1.getReg())) {
6088 .add(Src1);
6089 Src1.ChangeToRegister(Reg, false);
6107 if ((!Src1.isImm() && !Src1.isReg()) ||
6125 if (Src1.isImm())
6126 Src0.ChangeToImmediate(Src1.getImm());
6127 else if (Src1.isReg()) {
6128 Src0.ChangeToRegister(Src1.getReg(), false, false, Src1.isKill());
6129 Src0.setSubReg(Src1.getSubReg());
6133 Src1.ChangeToRegister(Src0Reg, false, false, Src0Kill);
6134 Src1.setSubReg(Src0SubReg);
6153 MachineOperand &Src1 = MI.getOperand(VOP3Idx[1]);
6156 if (Src1.isReg() && !RI.isSGPRClass(MRI.getRegClass(Src1.getReg()))) {
6159 .add(Src1);
6160 Src1.ChangeToRegister(Reg, false);
7408 MachineOperand &Src1 = Inst.getOperand(3);
7419 .add(Src1)
7785 MachineOperand &Src1 = Inst.getOperand(2);
7795 if (!IsSCC && Src0.isImm() && (Src0.getImm() == -1) && Src1.isImm() &&
7796 (Src1.getImm() == 0)) {
7841 .add(Src1) // False
7848 .add(Src1) // False
7893 MachineOperand &Src1 = Inst.getOperand(2);
7898 legalizeGenericOperand(MBB, MII, &AMDGPU::VGPR_32RegClass, Src1, MRI, DL);
7902 .add(Src1);
7913 bool Src1IsSGPR = Src1.isReg() &&
7914 RI.isSGPRClass(MRI.getRegClass(Src1.getReg()));
7926 .add(Src1);
7928 BuildMI(MBB, MII, DL, get(AMDGPU::S_NOT_B32), Temp).add(Src1);
7935 .add(Src1);
7959 MachineOperand &Src1 = Inst.getOperand(2);
7966 .add(Src1);
7988 MachineOperand &Src1 = Inst.getOperand(2);
7994 .add(Src1);
8080 MachineOperand &Src1 = Inst.getOperand(2);
8085 const TargetRegisterClass *Src1RC = MRI.getRegClass(Src1.getReg());
8100 buildExtractSubRegOrImm(MII, MRI, Src1, Src1RC, AMDGPU::sub0, Src1SubRC);
8104 buildExtractSubRegOrImm(MII, MRI, Src1, Src1RC, AMDGPU::sub1, Src1SubRC);
8189 MachineOperand &Src1 = Inst.getOperand(2);
8194 const TargetRegisterClass *Src1RC = MRI.getRegClass(Src1.getReg());
8209 buildExtractSubRegOrImm(MII, MRI, Src1, Src1RC, AMDGPU::sub0, Src1SubRC);
8248 MachineOperand &Src1 = Inst.getOperand(2);
8260 const TargetRegisterClass *Src1RC = Src1.isReg() ?
8261 MRI.getRegClass(Src1.getReg()) :
8269 MachineOperand SrcReg1Sub0 = buildExtractSubRegOrImm(MII, MRI, Src1, Src1RC,
8273 MachineOperand SrcReg1Sub1 = buildExtractSubRegOrImm(MII, MRI, Src1, Src1RC,
8315 MachineOperand &Src1 = Inst.getOperand(2);
8329 Op1 = &Src1;
8331 Op0 = &Src1;
8545 MachineOperand &Src1 = Inst.getOperand(2);
8563 .add(Src1)
8575 .add(Src1);
8584 .add(Src1)
8598 .add(Src1)