Lines Matching defs:Decoder
90 const MCDisassembler *Decoder) {
91 const auto *DAsm = static_cast<const AMDGPUDisassembler *>(Decoder);
102 const MCDisassembler *Decoder) {
103 const auto *DAsm = static_cast<const AMDGPUDisassembler *>(Decoder);
116 const MCDisassembler *Decoder) {
117 const auto *DAsm = static_cast<const AMDGPUDisassembler *>(Decoder);
123 const MCDisassembler *Decoder) {
124 const auto *DAsm = static_cast<const AMDGPUDisassembler *>(Decoder);
129 const MCDisassembler *Decoder) {
130 const auto *DAsm = static_cast<const AMDGPUDisassembler *>(Decoder);
137 const MCDisassembler *Decoder) { \
138 auto DAsm = static_cast<const AMDGPUDisassembler *>(Decoder); \
142 // Decoder for registers, decode directly using RegClassID. Imm(8-bit) is
147 const MCDisassembler *Decoder) { \
149 auto DAsm = static_cast<const AMDGPUDisassembler *>(Decoder); \
157 const MCDisassembler *Decoder) { \
159 auto DAsm = static_cast<const AMDGPUDisassembler *>(Decoder); \
170 const MCDisassembler *Decoder) {
172 const auto *DAsm = static_cast<const AMDGPUDisassembler *>(Decoder);
177 // Decoder for registers. Imm(7-bit) is number of register, uses decodeSrcOp to
182 // Decoder for registers. Imm(10-bit): Imm{7-0} is number of register,
188 const MCDisassembler *Decoder) {
190 false, 0, AMDGPU::OperandSemantics::INT, Decoder);
193 // Decoder for Src(9-bit encoding) registers only.
197 const MCDisassembler *Decoder) {
199 AMDGPU::OperandSemantics::INT, Decoder);
202 // Decoder for Src(9-bit encoding) AGPR, register number encoded in 9bits, set
207 const MCDisassembler *Decoder) {
209 AMDGPU::OperandSemantics::INT, Decoder);
212 // Decoder for 'enum10' from decodeSrcOp, Imm{0-8} is 9-bit Src encoding
217 const MCDisassembler *Decoder) {
219 AMDGPU::OperandSemantics::INT, Decoder);
222 // Decoder for RegisterOperands using 9-bit Src encoding. Operand can be
231 const MCDisassembler *Decoder) {
233 (AMDGPU::OperandSemantics)OperandSemantics, Decoder);
236 // Decoder for Src(9-bit encoding) AGPR or immediate. Set Imm{9} to 1 (set acc)
242 const MCDisassembler *Decoder) {
244 (AMDGPU::OperandSemantics)OperandSemantics, Decoder);
251 const MCDisassembler *Decoder) {
253 (AMDGPU::OperandSemantics)OperandSemantics, Decoder);
296 const MCDisassembler *Decoder) {
302 const auto *DAsm = static_cast<const AMDGPUDisassembler *>(Decoder);
308 const MCDisassembler *Decoder) {
313 const auto *DAsm = static_cast<const AMDGPUDisassembler *>(Decoder);
321 const MCDisassembler *Decoder) {
324 const auto *DAsm = static_cast<const AMDGPUDisassembler *>(Decoder);
340 const MCDisassembler *Decoder) {
341 const auto *DAsm = static_cast<const AMDGPUDisassembler *>(Decoder);
358 const MCDisassembler *Decoder) {
361 const auto *DAsm = static_cast<const AMDGPUDisassembler *>(Decoder);
374 const MCDisassembler *Decoder) {
378 const auto *DAsm = static_cast<const AMDGPUDisassembler *>(Decoder);
387 const MCDisassembler *Decoder) {
388 const auto *DAsm = static_cast<const AMDGPUDisassembler *>(Decoder);
393 uint64_t Addr, const void *Decoder) {
394 const auto *DAsm = static_cast<const AMDGPUDisassembler *>(Decoder);
414 const MCDisassembler *Decoder) {
415 const auto *DAsm = static_cast<const AMDGPUDisassembler *>(Decoder);
449 const MCDisassembler *Decoder) {
450 return decodeAVLdSt(Inst, Imm, Opw, Decoder);
455 const MCDisassembler *Decoder) {
457 const auto *DAsm = static_cast<const AMDGPUDisassembler *>(Decoder);
472 const MCDisassembler *Decoder) {
473 const auto *DAsm = static_cast<const AMDGPUDisassembler *>(Decoder);