Lines Matching defs:NumVecs

210   /// \p NumVecs is the number of vector destinations for the instruction.
212   bool selectVectorLoadIntrinsic(unsigned Opc, unsigned NumVecs,
214   bool selectVectorLoadLaneIntrinsic(unsigned Opc, unsigned NumVecs,
216   void selectVectorStoreIntrinsic(MachineInstr &I, unsigned NumVecs,
218   bool selectVectorStoreLaneIntrinsic(MachineInstr &I, unsigned NumVecs,
231   void SelectTable(MachineInstr &I, MachineRegisterInfo &MRI, unsigned NumVecs,
5983                                                            unsigned NumVecs,
5987   assert(NumVecs > 1 && NumVecs < 5 && "Only support 2, 3, or 4 vectors");
6000   for (unsigned Idx = 0; Idx < NumVecs; ++Idx) {
6012     unsigned Opc, unsigned NumVecs, MachineInstr &I) {
6015   assert(NumVecs > 1 && NumVecs < 5 && "Only support 2, 3, or 4 vectors");
6020   auto FirstSrcRegIt = I.operands_begin() + NumVecs + 1;
6021   SmallVector<Register, 4> Regs(NumVecs);
6022   std::transform(FirstSrcRegIt, FirstSrcRegIt + NumVecs, Regs.begin(),
6035   auto LaneNo = getIConstantVRegVal((FirstSrcRegIt + NumVecs)->getReg(), MRI);
6039   Register Ptr = (FirstSrcRegIt + NumVecs + 1)->getReg();
6048   for (unsigned Idx = 0; Idx < NumVecs; ++Idx) {
6065                                                             unsigned NumVecs,
6069   Register Ptr = I.getOperand(1 + NumVecs).getReg();
6071   SmallVector<Register, 2> Regs(NumVecs);
6072   std::transform(I.operands_begin() + 1, I.operands_begin() + 1 + NumVecs,
6083     MachineInstr &I, unsigned NumVecs, unsigned Opc) {
6088   SmallVector<Register, 2> Regs(NumVecs);
6089   std::transform(I.operands_begin() + 1, I.operands_begin() + 1 + NumVecs,
6101   auto LaneNo = getIConstantVRegVal(I.getOperand(1 + NumVecs).getReg(), MRI);
6104   Register Ptr = I.getOperand(1 + NumVecs + 1).getReg();