Lines Matching defs:MRI
113 bool earlySelectSHL(MachineInstr &I, MachineRegisterInfo &MRI);
117 MachineRegisterInfo &MRI);
119 bool convertPtrAddToAdd(MachineInstr &I, MachineRegisterInfo &MRI);
122 MachineRegisterInfo &MRI) const;
124 MachineRegisterInfo &MRI) const;
140 MachineRegisterInfo &MRI);
142 bool selectVectorAshrLshr(MachineInstr &I, MachineRegisterInfo &MRI);
143 bool selectVectorSHL(MachineInstr &I, MachineRegisterInfo &MRI);
156 MachineRegisterInfo &MRI) const;
176 MachineRegisterInfo &MRI);
194 MachineRegisterInfo &MRI);
197 bool tryOptBuildVecToSubregToReg(MachineInstr &MI, MachineRegisterInfo &MRI);
198 bool selectBuildVector(MachineInstr &I, MachineRegisterInfo &MRI);
199 bool selectMergeValues(MachineInstr &I, MachineRegisterInfo &MRI);
200 bool selectUnmergeValues(MachineInstr &I, MachineRegisterInfo &MRI);
202 bool selectShuffleVector(MachineInstr &I, MachineRegisterInfo &MRI);
203 bool selectExtractElt(MachineInstr &I, MachineRegisterInfo &MRI);
204 bool selectConcatVectors(MachineInstr &I, MachineRegisterInfo &MRI);
205 bool selectSplitVectorUnmerge(MachineInstr &I, MachineRegisterInfo &MRI);
221 MachineRegisterInfo &MRI);
222 bool selectIntrinsic(MachineInstr &I, MachineRegisterInfo &MRI);
223 bool selectJumpTable(MachineInstr &I, MachineRegisterInfo &MRI);
224 bool selectBrJT(MachineInstr &I, MachineRegisterInfo &MRI);
225 bool selectTLSGlobalValue(MachineInstr &I, MachineRegisterInfo &MRI);
227 MachineRegisterInfo &MRI) const;
228 bool selectReduction(MachineInstr &I, MachineRegisterInfo &MRI);
229 bool selectMOPS(MachineInstr &I, MachineRegisterInfo &MRI);
230 bool selectUSMovFromExtend(MachineInstr &I, MachineRegisterInfo &MRI);
231 void SelectTable(MachineInstr &I, MachineRegisterInfo &MRI, unsigned NumVecs,
234 bool selectIndexedExtLoad(MachineInstr &I, MachineRegisterInfo &MRI);
235 bool selectIndexedLoad(MachineInstr &I, MachineRegisterInfo &MRI);
236 bool selectIndexedStore(GIndexedStore &I, MachineRegisterInfo &MRI);
345 bool selectOverflowOp(MachineInstr &I, MachineRegisterInfo &MRI);
407 MachineRegisterInfo &MRI) const;
418 const MachineRegisterInfo &MRI) const;
421 const MachineRegisterInfo &MRI,
466 getExtendTypeForInst(MachineInstr &MI, MachineRegisterInfo &MRI,
750 auto &MRI = MF.getRegInfo();
758 getIConstantVRegValWithLookThrough(Root.getReg(), MRI, true);
775 const MachineRegisterInfo &MRI,
777 LLT Ty = MRI.getType(I.getOperand(0).getReg());
800 const RegisterBank *OpBank = RBI.getRegBank(MO.getReg(), MRI, TRI);
928 static bool copySubReg(MachineInstr &I, MachineRegisterInfo &MRI,
944 RBI.constrainGenericRegister(I.getOperand(0).getReg(), *To, MRI);
955 MachineRegisterInfo &MRI, const TargetRegisterInfo &TRI,
959 const RegisterBank &DstRegBank = *RBI.getRegBank(DstReg, MRI, TRI);
960 const RegisterBank &SrcRegBank = *RBI.getRegBank(SrcReg, MRI, TRI);
962 TypeSize DstSize = RBI.getSizeInBits(DstReg, MRI, TRI);
963 TypeSize SrcSize = RBI.getSizeInBits(SrcReg, MRI, TRI);
984 static bool selectDebugInstr(MachineInstr &I, MachineRegisterInfo &MRI,
994 LLT Ty = MRI.getType(Reg);
995 const RegClassOrRegBank &RegClassOrBank = MRI.getRegClassOrRegBank(Reg);
1007 RBI.constrainGenericRegister(Reg, *RC, MRI);
1014 MachineRegisterInfo &MRI, const TargetRegisterInfo &TRI,
1018 const RegisterBank &DstRegBank = *RBI.getRegBank(DstReg, MRI, TRI);
1019 const RegisterBank &SrcRegBank = *RBI.getRegBank(SrcReg, MRI, TRI);
1024 std::tie(SrcRC, DstRC) = getRegClassesForCopy(I, TII, MRI, TRI, RBI);
1028 << RBI.getSizeInBits(DstReg, MRI, TRI) << '\n');
1053 copySubReg(I, MRI, RBI, Copy.getReg(0), DstRC, SubReg);
1060 copySubReg(I, MRI, RBI, SrcReg, DstRC, SubReg);
1068 Register PromoteReg = MRI.createVirtualRegister(PromotionRC);
1086 if (!RBI.constrainGenericRegister(DstReg, *DstRC, MRI)) {
1097 return selectCopy(I, TII, MRI, TRI, RBI);
1184 MachineRegisterInfo &MRI = *MIB.getMRI();
1185 assert(RBI.getRegBank(False, MRI, TRI)->getID() ==
1186 RBI.getRegBank(True, MRI, TRI)->getID() &&
1188 LLT Ty = MRI.getType(True);
1195 if (RBI.getRegBank(True, MRI, TRI)->getID() != AArch64::GPRRegBankID) {
1205 auto TryFoldBinOpIntoSelect = [&Opc, Is32Bit, &CC, &MRI,
1219 if (mi_match(Reg, MRI, m_Neg(m_Reg(MatchReg)))) {
1236 if (mi_match(Reg, MRI, m_Not(m_Reg(MatchReg)))) {
1253 if (mi_match(Reg, MRI,
1272 auto TryOptSelectCst = [&Opc, &True, &False, &CC, Is32Bit, &MRI,
1276 auto TrueCst = getIConstantVRegValWithLookThrough(True, MRI);
1277 auto FalseCst = getIConstantVRegValWithLookThrough(False, MRI);
1464 MachineRegisterInfo &MRI) {
1467 while (MachineInstr *MI = getDefIgnoringCopies(Reg, MRI)) {
1471 !MRI.hasOneNonDBGUse(MI->getOperand(0).getReg()))
1485 if (!NextReg.isValid() || !MRI.hasOneNonDBGUse(NextReg))
1503 auto VRegAndVal = getIConstantVRegValWithLookThrough(ConstantReg, MRI);
1509 VRegAndVal = getIConstantVRegValWithLookThrough(ConstantReg, MRI);
1524 getIConstantVRegValWithLookThrough(MI->getOperand(2).getReg(), MRI);
1538 unsigned TestRegSize = MRI.getType(TestReg).getSizeInBits();
1600 MachineRegisterInfo &MRI = *MIB.getMRI();
1603 TestReg = getTestBitReg(TestReg, Bit, IsNegative, MRI);
1604 LLT Ty = MRI.getType(TestReg);
1673 MachineRegisterInfo &MRI = *MIB.getMRI();
1674 assert(RBI.getRegBank(CompareReg, MRI, TRI)->getID() ==
1677 auto Ty = MRI.getType(CompareReg);
1720 MachineRegisterInfo &MRI = *MIB.getMRI();
1728 auto VRegAndVal = getIConstantVRegValWithLookThrough(RHS, MRI);
1729 MachineInstr *AndInst = getOpcodeDef(TargetOpcode::G_AND, LHS, MRI);
1742 uint64_t Bit = MRI.getType(LHS).getSizeInBits() - 1;
1751 uint64_t Bit = MRI.getType(LHS).getSizeInBits() - 1;
1760 uint64_t Bit = MRI.getType(LHS).getSizeInBits() - 1;
1772 VRegAndVal = getIConstantVRegValWithLookThrough(RHS, MRI);
1773 AndInst = getOpcodeDef(TargetOpcode::G_AND, LHS, MRI);
1791 auto LHSTy = MRI.getType(LHS);
1822 MachineInstr &I, MachineFunction &MF, MachineRegisterInfo &MRI) {
1824 MachineInstr *CCMI = MRI.getVRegDef(CondReg);
1857 MachineRegisterInfo &MRI) {
1858 assert(MRI.getType(Reg).isVector() && "Expected a *vector* shift operand");
1859 MachineInstr *OpMI = MRI.getVRegDef(Reg);
1860 return getAArch64VectorSplatScalar(*OpMI, MRI);
1866 MachineRegisterInfo &MRI) {
1867 std::optional<int64_t> ShiftImm = getVectorShiftImm(Reg, MRI);
1899 MachineRegisterInfo &MRI) {
1902 const LLT Ty = MRI.getType(DstReg);
1911 std::optional<int64_t> ImmVal = getVectorSHLImm(Ty, Src2Reg, MRI);
1944 MachineInstr &I, MachineRegisterInfo &MRI) {
1948 const LLT Ty = MRI.getType(DstReg);
2003 MachineInstr &I, MachineFunction &MF, MachineRegisterInfo &MRI) const {
2039 const Register Top = MRI.createVirtualRegister(PtrRegClass);
2075 const Register Temp = MRI.createVirtualRegister(&AArch64::GPR32RegClass);
2107 MachineInstr &I, MachineFunction &MF, MachineRegisterInfo &MRI) const {
2111 Register ArgsAddrReg = MRI.createVirtualRegister(&AArch64::GPR64RegClass);
2145 MachineRegisterInfo &MRI = MF.getRegInfo();
2158 : MRI.createVirtualRegister(&AArch64::GPR64RegClass);
2181 MachineRegisterInfo &MRI = MF.getRegInfo();
2185 bool Changed = contractCrossBankCopyIntoStore(I, MRI);
2187 if (MRI.getType(SrcOp.getReg()).isPointer()) {
2194 RBI.constrainGenericRegister(NewSrc, AArch64::GPR64RegClass, MRI);
2200 return convertPtrAddToAdd(I, MRI);
2207 const LLT DstTy = MRI.getType(DstReg);
2210 MRI.setType(DstReg, LLT::scalar(64));
2215 LLT DstTy = MRI.getType(I.getOperand(0).getReg());
2219 MRI.setType(I.getOperand(0).getReg(),
2221 MRI.setRegClass(NewSrc.getReg(0), &AArch64::GPR64RegClass);
2227 LLT DstTy = MRI.getType(I.getOperand(0).getReg());
2228 LLT SrcVecTy = MRI.getType(I.getOperand(1).getReg());
2232 MRI.setType(I.getOperand(1).getReg(),
2234 MRI.setType(I.getOperand(0).getReg(),
2236 MRI.setRegClass(NewSrc.getReg(0), &AArch64::GPR64RegClass);
2247 LLT SrcTy = MRI.getType(SrcReg);
2248 LLT DstTy = MRI.getType(I.getOperand(0).getReg());
2252 if (RBI.getRegBank(SrcReg, MRI, TRI)->getID() == AArch64::FPRRegBankID) {
2275 MachineInstr &I, MachineRegisterInfo &MRI) {
2279 const LLT PtrTy = MRI.getType(DstReg);
2288 MRI.setRegBank(PtrToInt.getReg(0), RBI.getRegBank(AArch64::FPRRegBankID));
2290 MRI.setRegBank(PtrToInt.getReg(0), RBI.getRegBank(AArch64::GPRRegBankID));
2295 MRI.setType(DstReg, CastPtrTy);
2305 if (!mi_match(I.getOperand(2).getReg(), MRI, m_Neg(m_Reg(NegatedReg))))
2313 MachineRegisterInfo &MRI) {
2319 auto VRegAndVal = getIConstantVRegVal(MO.getReg(), MRI);
2323 const LLT DstTy = MRI.getType(I.getOperand(0).getReg());
2347 MachineInstr &I, MachineRegisterInfo &MRI) {
2363 Register DefDstReg = getSrcRegIgnoringCopies(I.getOperand(0).getReg(), MRI);
2366 LLT DefDstTy = MRI.getType(DefDstReg);
2368 LLT StoreSrcTy = MRI.getType(StoreSrcReg);
2379 if (RBI.getRegBank(StoreSrcReg, MRI, TRI) ==
2380 RBI.getRegBank(DefDstReg, MRI, TRI))
2394 MachineRegisterInfo &MRI = MF.getRegInfo();
2401 auto ValAndVReg = getAnyConstantVRegValWithLookThrough(Src, MRI);
2407 MRI.getType(Dst).getNumElements(),
2409 Type::getIntNTy(Ctx, MRI.getType(Dst).getScalarSizeInBits()),
2410 ValAndVReg->Value.trunc(MRI.getType(Dst).getScalarSizeInBits())));
2411 if (!emitConstantVector(Dst, CV, MIB, MRI))
2419 if (selectUSMovFromExtend(I, MRI))
2425 return earlySelectSHL(I, MRI);
2437 LLT Ty = MRI.getType(DefReg);
2440 RBI.constrainGenericRegister(DefReg, AArch64::GPR64RegClass, MRI);
2443 RBI.constrainGenericRegister(DefReg, AArch64::GPR32RegClass, MRI);
2464 LLT Ty = MRI.getType(AddLHS);
2473 if (!MRI.hasOneNonDBGUse(Reg))
2478 return getOpcodeDef(TargetOpcode::G_ICMP, Reg, MRI);
2482 if (!mi_match(Reg, MRI,
2485 auto *Cmp = getOpcodeDef(TargetOpcode::G_ICMP, ZExt, MRI);
2487 MRI.getType(Cmp->getOperand(2).getReg()).getSizeInBits() != 64)
2517 LLT Ty = MRI.getType(Dst);
2531 Dst, MRI,
2566 MachineRegisterInfo &MRI = MF.getRegInfo();
2587 const LLT DefTy = MRI.getType(DefReg);
2590 MRI.getRegClassOrRegBank(DefReg);
2609 return RBI.constrainGenericRegister(DefReg, *DefRC, MRI);
2613 return selectCopy(I, TII, MRI, TRI, RBI);
2616 return selectDebugInstr(I, MRI, RBI);
2647 I.getOperand(0).isReg() ? MRI.getType(I.getOperand(0).getReg()) : LLT{};
2659 getIConstantVRegValWithLookThrough(I.getOperand(2).getReg(), MRI);
2662 getIConstantVRegValWithLookThrough(I.getOperand(3).getReg(), MRI);
2674 return selectCompareBranch(I, MF, MRI);
2692 return selectBrJT(I, MRI);
2699 MachineInstr *BaseMI = MRI.getVRegDef(I.getOperand(1).getReg());
2730 const LLT DefTy = MRI.getType(DefReg);
2732 const RegisterBank &RB = *RBI.getRegBank(DefReg, MRI, TRI);
2800 return RBI.constrainGenericRegister(DefReg, FPRRC, MRI);
2806 const Register DefGPRReg = MRI.createVirtualRegister(
2813 if (!RBI.constrainGenericRegister(DefReg, FPRRC, MRI)) {
2839 LLT SrcTy = MRI.getType(SrcReg);
2840 LLT DstTy = MRI.getType(DstReg);
2857 const RegisterBank &SrcRB = *RBI.getRegBank(SrcReg, MRI, TRI);
2858 const RegisterBank &DstRB = *RBI.getRegBank(DstReg, MRI, TRI);
2866 constrainOperandRegClass(MF, TRI, MRI, TII, RBI, *NewI,
2893 DstReg = MRI.createGenericVirtualRegister(LLT::scalar(64));
2898 AArch64::GPR32RegClass, MRI);
2905 LLT SrcTy = MRI.getType(I.getOperand(2).getReg());
2906 LLT DstTy = MRI.getType(I.getOperand(0).getReg());
2915 unsigned Width = MRI.getType(I.getOperand(2).getReg()).getSizeInBits();
2925 Register SrcReg = MRI.createGenericVirtualRegister(LLT::scalar(64));
2933 AArch64::GPR32RegClass, MRI);
2964 return selectTLSGlobalValue(I, MRI);
2993 return selectPtrAuthGlobalValue(I, MRI);
3000 LLT PtrTy = MRI.getType(LdSt.getPointerReg());
3034 if (MRI.getType(ValReg).getSizeInBits() == 64 && MemSizeInBits != 64) {
3036 Register NewVal = MRI.createVirtualRegister(&AArch64::GPR32RegClass);
3049 const RegisterBank &PtrRB = *RBI.getRegBank(PtrReg, MRI, TRI);
3053 assert(MRI.getType(PtrReg).isPointer() &&
3058 const RegisterBank &RB = *RBI.getRegBank(ValReg, MRI, TRI);
3059 LLT ValTy = MRI.getType(ValReg);
3074 RBI.constrainGenericRegister(Copy, *RC, MRI);
3087 MRI.createGenericVirtualRegister(LdSt.getMMO().getMemoryType());
3089 MRI.setRegBank(NewDst, RB);
3096 auto SubRegRC = getRegClassForTypeOnBank(MRI.getType(OldDst), RB);
3097 RBI.constrainGenericRegister(OldDst, *SubRegRC, MRI);
3139 LoadStore->getOperand(0).getReg(), MRI);
3158 if (MRI.getType(LoadStore->getOperand(0).getReg()).getSizeInBits() != 64)
3162 Register LdReg = MRI.createVirtualRegister(&AArch64::GPR32RegClass);
3173 MRI);
3180 return selectIndexedExtLoad(I, MRI);
3182 return selectIndexedLoad(I, MRI);
3184 return selectIndexedStore(cast<GIndexedStore>(I), MRI);
3188 if (MRI.getType(I.getOperand(0).getReg()).isVector())
3189 return selectVectorAshrLshr(I, MRI);
3193 MRI.getType(I.getOperand(0).getReg()).isVector())
3194 return selectVectorSHL(I, MRI);
3203 const LLT ShiftTy = MRI.getType(ShiftReg);
3204 const LLT SrcTy = MRI.getType(SrcReg);
3211 MRI.setRegBank(Trunc.getReg(0), RBI.getRegBank(AArch64::GPRRegBankID));
3218 if (unsupportedBinOp(I, RBI, MRI, TRI))
3224 const RegisterBank &RB = *RBI.getRegBank(DefReg, MRI, TRI);
3252 return selectOverflowOp(I, MRI);
3256 std::optional<int64_t> MaskVal = getIConstantVRegSExtVal(MaskReg, MRI);
3270 const LLT DstTy = MRI.getType(I.getOperand(0).getReg());
3271 const LLT SrcTy = MRI.getType(I.getOperand(1).getReg());
3276 const RegisterBank &DstRB = *RBI.getRegBank(DstReg, MRI, TRI);
3277 const RegisterBank &SrcRB = *RBI.getRegBank(SrcReg, MRI, TRI);
3294 if (!RBI.constrainGenericRegister(SrcReg, *SrcRC, MRI) ||
3295 !RBI.constrainGenericRegister(DstReg, *DstRC, MRI)) {
3338 return selectCopy(I, TII, MRI, TRI, RBI);
3346 if (selectUSMovFromExtend(I, MRI))
3352 const RegisterBank &RBDst = *RBI.getRegBank(DstReg, MRI, TRI);
3359 const RegisterBank &RBSrc = *RBI.getRegBank(SrcReg, MRI, TRI);
3366 const unsigned DstSize = MRI.getType(DstReg).getSizeInBits();
3381 Register ExtSrc = MRI.createVirtualRegister(&AArch64::GPR64allRegClass);
3389 return selectCopy(I, TII, MRI, TRI, RBI);
3395 if (selectUSMovFromExtend(I, MRI))
3402 const LLT DstTy = MRI.getType(DefReg);
3403 const LLT SrcTy = MRI.getType(SrcReg);
3415 assert((*RBI.getRegBank(DefReg, MRI, TRI)).getID() ==
3428 auto *LoadMI = getOpcodeDef(TargetOpcode::G_LOAD, SrcReg, MRI);
3430 RBI.getRegBank(SrcReg, MRI, TRI)->getID() == AArch64::GPRRegBankID;
3435 return selectCopy(I, TII, MRI, TRI, RBI);
3442 MRI.createVirtualRegister(&AArch64::GPR32RegClass);
3453 MRI)) {
3459 MRI)) {
3473 MRI)) {
3508 const LLT DstTy = MRI.getType(I.getOperand(0).getReg()),
3509 SrcTy = MRI.getType(I.getOperand(1).getReg());
3522 return selectCopy(I, TII, MRI, TRI, RBI);
3527 return selectCopy(I, TII, MRI, TRI, RBI);
3535 return selectCopy(I, TII, MRI, TRI, RBI);
3548 Register DeadVReg = MRI.createVirtualRegister(&AArch64::GPR32RegClass);
3588 return STI.isTargetDarwin() ? selectVaStartDarwin(I, MF, MRI)
3589 : selectVaStartAAPCS(I, MF, MRI);
3591 return selectIntrinsic(I, MRI);
3593 return selectIntrinsicWithSideEffects(I, MRI);
3596 const LLT DstTy = MRI.getType(I.getOperand(0).getReg());
3598 const RegisterBank &DstRB = *RBI.getRegBank(DstReg, MRI, TRI);
3600 RBI.constrainGenericRegister(DstReg, *DstRC, MRI);
3617 AArch64::GPR64RegClass, MRI);
3644 if (RBI.getRegBank(I.getOperand(1).getReg(), MRI, TRI)->getID() !=
3647 LLT VecTy = MRI.getType(I.getOperand(0).getReg());
3661 return selectBuildVector(I, MRI);
3663 return selectMergeValues(I, MRI);
3665 return selectUnmergeValues(I, MRI);
3667 return selectShuffleVector(I, MRI);
3669 return selectExtractElt(I, MRI);
3671 return selectConcatVectors(I, MRI);
3673 return selectJumpTable(I, MRI);
3679 return selectMOPS(I, MRI);
3693 MachineRegisterInfo &MRI) {
3714 const Register DstPtrCopy = MRI.cloneVirtualRegister(DstPtr.getReg());
3715 const Register SrcValCopy = MRI.cloneVirtualRegister(SrcOrVal.getReg());
3716 const Register SizeCopy = MRI.cloneVirtualRegister(Size.getReg());
3723 RBI.constrainGenericRegister(DstPtrCopy, AArch64::GPR64commonRegClass, MRI);
3724 RBI.constrainGenericRegister(SrcValCopy, SrcValRegClass, MRI);
3725 RBI.constrainGenericRegister(SizeCopy, AArch64::GPR64RegClass, MRI);
3735 Register DefDstPtr = MRI.createVirtualRegister(&AArch64::GPR64commonRegClass);
3736 Register DefSize = MRI.createVirtualRegister(&AArch64::GPR64RegClass);
3741 Register DefSrcPtr = MRI.createVirtualRegister(&SrcValRegClass);
3751 MachineRegisterInfo &MRI) {
3781 Register TargetReg = MRI.createVirtualRegister(&AArch64::GPR64RegClass);
3782 Register ScratchReg = MRI.createVirtualRegister(&AArch64::GPR64spRegClass);
3797 MachineRegisterInfo &MRI) {
3813 MachineInstr &I, MachineRegisterInfo &MRI) {
3851 MRI);
3888 MachineRegisterInfo &MRI) const {
3889 LLT DstTy = MRI.getType(DstReg);
3891 getRegClassForTypeOnBank(DstTy, *RBI.getRegBank(SrcReg, MRI, TRI));
3906 RBI.constrainGenericRegister(DstReg, *RC, MRI);
3911 MachineInstr &I, MachineRegisterInfo &MRI) {
3913 const LLT DstTy = MRI.getType(I.getOperand(0).getReg());
3914 const LLT SrcTy = MRI.getType(I.getOperand(1).getReg());
3916 const RegisterBank &RB = *RBI.getRegBank(I.getOperand(1).getReg(), MRI, TRI);
3950 Register SubToRegDef = MRI.createVirtualRegister(DstRC);
3957 Register SubToRegDef2 = MRI.createVirtualRegister(DstRC);
4011 MachineRegisterInfo &MRI = *MIRBuilder.getMRI();
4027 const RegisterBank &VecRB = *RBI.getRegBank(VecReg, MRI, TRI);
4028 const LLT &VecTy = MRI.getType(VecReg);
4039 DstReg = MRI.createVirtualRegister(DstRC);
4044 RBI.constrainGenericRegister(*DstReg, *DstRC, MRI);
4064 RBI.constrainGenericRegister(*DstReg, *DstRC, MRI);
4069 MachineInstr &I, MachineRegisterInfo &MRI) {
4073 const LLT NarrowTy = MRI.getType(DstReg);
4075 const LLT WideTy = MRI.getType(SrcReg);
4085 if (RBI.getRegBank(DstReg, MRI, TRI)->getID() != AArch64::FPRRegBankID) {
4091 auto VRegAndVal = getIConstantVRegValWithLookThrough(LaneIdxOp.getReg(), MRI);
4097 const RegisterBank &DstRB = *RBI.getRegBank(DstReg, MRI, TRI);
4108 MachineInstr &I, MachineRegisterInfo &MRI) {
4111 const LLT NarrowTy = MRI.getType(I.getOperand(0).getReg());
4112 const LLT SrcTy = MRI.getType(SrcReg);
4123 *RBI.getRegBank(I.getOperand(0).getReg(), MRI, TRI);
4136 MachineRegisterInfo &MRI) {
4141 if (RBI.getRegBank(I.getOperand(0).getReg(), MRI, TRI)->getID() !=
4143 RBI.getRegBank(I.getOperand(1).getReg(), MRI, TRI)->getID() !=
4154 const LLT NarrowTy = MRI.getType(I.getOperand(0).getReg());
4155 const LLT WideTy = MRI.getType(SrcReg);
4163 return selectSplitVectorUnmerge(I, MRI);
4191 *RBI.getRegBank(SrcReg, MRI, TRI));
4197 Register ImpDefReg = MRI.createVirtualRegister(&AArch64::FPR128RegClass);
4203 Register InsertReg = MRI.createVirtualRegister(&AArch64::FPR128RegClass);
4244 MRI.getRegClassOrNull(I.getOperand(1).getReg());
4250 RBI.constrainGenericRegister(CopyTo, *RC, MRI);
4256 MachineInstr &I, MachineRegisterInfo &MRI) {
4394 MachineRegisterInfo &MRI = MIRBuilder.getMF().getRegInfo();
4396 auto Ty = MRI.getType(LHS.getReg());
4469 MachineRegisterInfo *MRI = MIRBuilder.getMRI();
4470 bool Is32Bit = (MRI->getType(LHS.getReg()).getSizeInBits() == 32);
4480 MachineRegisterInfo *MRI = MIRBuilder.getMRI();
4481 bool Is32Bit = (MRI->getType(LHS.getReg()).getSizeInBits() == 32);
4489 MachineRegisterInfo &MRI = MIRBuilder.getMF().getRegInfo();
4490 bool Is32Bit = (MRI.getType(LHS.getReg()).getSizeInBits() == 32);
4492 return emitADDS(MRI.createVirtualRegister(RC), LHS, RHS, MIRBuilder);
4499 MachineRegisterInfo &MRI = MIRBuilder.getMF().getRegInfo();
4500 LLT Ty = MRI.getType(LHS.getReg());
4508 if (auto ValAndVReg = getIConstantVRegValWithLookThrough(RHS.getReg(), MRI)) {
4529 MachineRegisterInfo &MRI = MIRBuilder.getMF().getRegInfo();
4530 LLT CmpTy = MRI.getType(LHS.getReg());
4538 auto Dst = MRI.cloneVirtualRegister(LHS.getReg());
4544 MachineRegisterInfo &MRI = *MIRBuilder.getMRI();
4546 LLT Ty = MRI.getType(Dst);
4558 Register Def1Reg = MRI.createVirtualRegister(RC);
4559 Register Def2Reg = MRI.createVirtualRegister(RC);
4571 MachineRegisterInfo &MRI = *MIRBuilder.getMRI();
4572 LLT Ty = MRI.getType(LHS);
4580 const ConstantFP *FPImm = getConstantFPVRegVal(RHS, MRI);
4589 const ConstantFP *LHSImm = getConstantFPVRegVal(LHS, MRI);
4618 MachineRegisterInfo &MRI = MIRBuilder.getMF().getRegInfo();
4620 const LLT Op1Ty = MRI.getType(Op1);
4621 const LLT Op2Ty = MRI.getType(Op2);
4641 const RegisterBank &FPRBank = *RBI.getRegBank(Op1, MRI, TRI);
4660 Dst = MRI.createVirtualRegister(DstRC);
4675 auto &MRI = *MIRBuilder.getMRI();
4676 const RegClassOrRegBank &RegClassOrBank = MRI.getRegClassOrRegBank(Dst);
4683 Size = MRI.getType(Dst).getSizeInBits();
4695 MachineRegisterInfo *MRI = MIB.getMRI();
4710 MachineInstr *SrcMI = MRI->getVRegDef(CarryReg);
4722 Register DeadReg = MRI->createVirtualRegister(&AArch64::GPR32RegClass);
4736 MachineRegisterInfo &MRI) {
4751 if (!MRI.use_nodbg_empty(CarryOutReg)) {
4807 bool WillNegate, MachineRegisterInfo &MRI,
4809 if (!MRI.hasOneNonDBGUse(Val))
4811 MachineInstr *ValDef = MRI.getVRegDef(Val);
4827 if (!canEmitConjunction(O0, CanNegateL, MustBeFirstL, IsOR, MRI, Depth + 1))
4831 if (!canEmitConjunction(O1, CanNegateR, MustBeFirstR, IsOR, MRI, Depth + 1))
4863 auto &MRI = *MIB.getMRI();
4864 LLT OpTy = MRI.getType(LHS);
4869 C = getIConstantVRegValWithLookThrough(RHS, MRI);
4913 auto &MRI = *MIB.getMRI();
4914 MachineInstr *ValDef = MRI.getVRegDef(Val);
4944 auto Dst = MRI.cloneVirtualRegister(LHS);
4953 assert(MRI.hasOneNonDBGUse(Val) && "Valid conjunction/disjunction tree");
4960 bool ValidL = canEmitConjunction(LHS, CanNegateL, MustBeFirstL, IsOR, MRI);
4967 bool ValidR = canEmitConjunction(RHS, CanNegateR, MustBeFirstR, IsOR, MRI);
5046 MachineRegisterInfo &MRI = *MIB.getMRI();
5065 MachineInstr *CondDef = MRI.getVRegDef(I.getOperand(1).getReg());
5069 if (!MRI.hasOneNonDBGUse(CondDefReg)) {
5071 for (const MachineInstr &UI : MRI.use_nodbg_instructions(CondDefReg)) {
5127 MachineRegisterInfo &MRI = *MIRBuilder.getMRI();
5138 MachineInstr *LHSDef = getDefIgnoringCopies(LHS.getReg(), MRI);
5139 MachineInstr *RHSDef = getDefIgnoringCopies(RHS.getReg(), MRI);
5149 if (isCMN(LHSDef, P, MRI))
5162 if (isCMN(RHSDef, P, MRI))
5176 auto ValAndVReg = getIConstantVRegValWithLookThrough(RHS.getReg(), MRI);
5188 MachineInstr &I, MachineRegisterInfo &MRI) {
5189 const LLT DstTy = MRI.getType(I.getOperand(0).getReg());
5191 const LLT Src1Ty = MRI.getType(Src1Reg);
5193 const LLT Src2Ty = MRI.getType(Src2Reg);
5251 RBI.constrainGenericRegister(Copy.getReg(0), AArch64::FPR64RegClass, MRI);
5273 MachineRegisterInfo &MRI = *MIRBuilder.getMRI();
5277 DstReg = MRI.createVirtualRegister(DstRC);
5279 unsigned EltSize = MRI.getType(EltReg).getSizeInBits();
5299 MachineInstr &MI, MachineRegisterInfo &MRI) {
5306 const LLT DstTy = MRI.getType(DefReg);
5313 MI.getOperand(1).getReg(), MRI);
5315 if (!Extract || !mi_match(Extract->getOperand(2).getReg(), MRI, m_ICst(Lane)))
5319 const LLT VecTy = MRI.getType(Src0);
5350 Register NewReg = MRI.createVirtualRegister(&AArch64::GPR32RegClass);
5356 RBI.constrainGenericRegister(DefReg, AArch64::GPR64RegClass, MRI);
5535 MachineInstr &MI, MachineRegisterInfo &MRI) {
5541 LLT Ty = MRI.getType(Dst);
5591 if (RBI.getRegBank(Dst, MRI, TRI)->getID() == AArch64::FPRRegBankID)
5594 auto Cst = getIConstantVRegVal(Offset, MRI);
5611 MRI);
5614 selectCopy(*Copy, TII, MRI, TRI, RBI);
5622 MachineRegisterInfo &MRI) {
5628 assert(MRI.getType(Dst).getSizeInBits() <= 128 &&
5632 if (MemSize < MRI.getType(Dst).getSizeInBytes())
5633 return selectIndexedExtLoad(MI, MRI);
5643 if (RBI.getRegBank(Dst, MRI, TRI)->getID() == AArch64::FPRRegBankID)
5654 if (RBI.getRegBank(Dst, MRI, TRI)->getID() == AArch64::FPRRegBankID)
5659 auto Cst = getIConstantVRegVal(Offset, MRI);
5671 MachineRegisterInfo &MRI) {
5676 LLT ValTy = MRI.getType(Val);
5688 if (RBI.getRegBank(Val, MRI, TRI)->getID() == AArch64::FPRRegBankID)
5700 if (RBI.getRegBank(Val, MRI, TRI)->getID() == AArch64::FPRRegBankID)
5706 auto Cst = getIConstantVRegVal(Offset, MRI);
5720 MachineRegisterInfo &MRI) {
5721 LLT DstTy = MRI.getType(Dst);
5738 RBI.constrainGenericRegister(Dst, AArch64::FPR64RegClass, MRI);
5788 Register NewDst = MRI.createVirtualRegister(&AArch64::FPR128RegClass);
5810 Dst, *MRI.getRegClass(CPLoad->getOperand(0).getReg()), MRI);
5815 MachineInstr &I, LLT DstTy, MachineRegisterInfo &MRI) {
5827 getOpcodeDef(TargetOpcode::G_CONSTANT, I.getOperand(Idx).getReg(), MRI);
5832 I.getOperand(Idx).getReg(), MRI)))
5839 if (!emitConstantVector(I.getOperand(0).getReg(), CV, MIB, MRI))
5846 MachineInstr &I, MachineRegisterInfo &MRI) {
5853 LLT EltTy = MRI.getType(EltReg);
5856 const RegisterBank &EltRB = *RBI.getRegBank(EltReg, MRI, TRI);
5857 const RegisterBank &DstRB = *RBI.getRegBank(Dst, MRI, TRI);
5860 if (any_of(drop_begin(I.operands(), 2), [&MRI](const MachineOperand &Op) {
5861 return !getOpcodeDef(TargetOpcode::G_IMPLICIT_DEF, Op.getReg(), MRI);
5869 getRegClassForTypeOnBank(MRI.getType(Dst), DstRB);
5880 return RBI.constrainGenericRegister(Dst, *DstRC, MRI);
5884 MachineRegisterInfo &MRI) {
5888 const LLT DstTy = MRI.getType(I.getOperand(0).getReg());
5889 const LLT EltTy = MRI.getType(I.getOperand(1).getReg());
5892 if (tryOptConstantBuildVec(I, DstTy, MRI))
5894 if (tryOptBuildVecToSubregToReg(I, MRI))
5899 const RegisterBank &RB = *RBI.getRegBank(I.getOperand(1).getReg(), MRI, TRI);
5919 if (!getOpcodeDef<GImplicitDef>(OpReg, MRI)) {
5930 getRegClassForTypeOnBank(DstTy, *RBI.getRegBank(DstVec, MRI, TRI));
5947 Register Reg = MRI.createVirtualRegister(RC);
5953 RBI.constrainGenericRegister(DstReg, *RC, MRI);
5973 getRegClassForTypeOnBank(DstTy, *RBI.getRegBank(DstVec, MRI, TRI));
5974 RBI.constrainGenericRegister(DstReg, *RC, MRI);
5988 auto &MRI = *MIB.getMRI();
5989 LLT Ty = MRI.getType(I.getOperand(0).getReg());
5995 assert(MRI.getType(Ptr).isPointer() && "Expected a pointer type?");
6006 selectCopy(*Vec, TII, MRI, TRI, RBI);
6016 auto &MRI = *MIB.getMRI();
6017 LLT Ty = MRI.getType(I.getOperand(0).getReg());
6035 auto LaneNo = getIConstantVRegVal((FirstSrcRegIt + NumVecs)->getReg(), MRI);
6056 selectCopy(*Vec, TII, MRI, TRI, RBI);
6058 !emitNarrowVector(I.getOperand(Idx).getReg(), WideReg, MIB, MRI))
6067 MachineRegisterInfo &MRI = I.getParent()->getParent()->getRegInfo();
6068 LLT Ty = MRI.getType(I.getOperand(1).getReg());
6084 MachineRegisterInfo &MRI = I.getParent()->getParent()->getRegInfo();
6085 LLT Ty = MRI.getType(I.getOperand(1).getReg());
6101 auto LaneNo = getIConstantVRegVal(I.getOperand(1 + NumVecs).getReg(), MRI);
6115 MachineInstr &I, MachineRegisterInfo &MRI) {
6139 LLT Ty = MRI.getType(I.getOperand(0).getReg());
6163 LLT Ty = MRI.getType(I.getOperand(0).getReg());
6187 LLT Ty = MRI.getType(I.getOperand(0).getReg());
6211 LLT Ty = MRI.getType(I.getOperand(0).getReg());
6235 LLT Ty = MRI.getType(I.getOperand(0).getReg());
6253 LLT Ty = MRI.getType(I.getOperand(0).getReg());
6277 LLT Ty = MRI.getType(I.getOperand(0).getReg());
6301 LLT Ty = MRI.getType(I.getOperand(0).getReg());
6319 LLT Ty = MRI.getType(I.getOperand(0).getReg());
6343 LLT Ty = MRI.getType(I.getOperand(0).getReg());
6367 LLT Ty = MRI.getType(I.getOperand(0).getReg());
6385 LLT Ty = MRI.getType(I.getOperand(0).getReg());
6409 LLT Ty = MRI.getType(I.getOperand(1).getReg());
6433 LLT Ty = MRI.getType(I.getOperand(1).getReg());
6457 LLT Ty = MRI.getType(I.getOperand(1).getReg());
6481 LLT Ty = MRI.getType(I.getOperand(1).getReg());
6505 LLT Ty = MRI.getType(I.getOperand(1).getReg());
6529 LLT Ty = MRI.getType(I.getOperand(1).getReg());
6553 LLT Ty = MRI.getType(I.getOperand(1).getReg());
6571 LLT Ty = MRI.getType(I.getOperand(1).getReg());
6589 LLT Ty = MRI.getType(I.getOperand(1).getReg());
6628 Register SizeDef = MRI.createGenericVirtualRegister(LLT::scalar(64));
6643 MachineRegisterInfo &MRI) {
6654 if (MRI.getType(DstReg).getSizeInBits() != 32 ||
6655 MRI.getType(SrcReg).getSizeInBits() != 32)
6660 if (RBI.getRegBank(SrcReg, MRI, TRI)->getID() != AArch64::FPRRegBankID) {
6661 SrcReg = MRI.createVirtualRegister(&AArch64::FPR32RegClass);
6666 AArch64::GPR32RegClass, MRI);
6669 if (RBI.getRegBank(DstReg, MRI, TRI)->getID() != AArch64::FPRRegBankID)
6670 DstReg = MRI.createVirtualRegister(&AArch64::FPR32RegClass);
6682 AArch64::GPR32RegClass, MRI);
6699 extractPtrauthBlendDiscriminators(AUTDisc, MRI);
6704 extractPtrauthBlendDiscriminators(PACDisc, MRI);
6718 RBI.constrainGenericRegister(DstReg, AArch64::GPR64RegClass, MRI);
6731 extractPtrauthBlendDiscriminators(AUTDisc, MRI);
6742 RBI.constrainGenericRegister(DstReg, AArch64::GPR64RegClass, MRI);
6753 RBI.constrainGenericRegister(DstReg, AArch64::GPR64RegClass, MRI);
6779 Register NextFrame = MRI.createVirtualRegister(&AArch64::GPR64spRegClass);
6792 Register TmpReg = MRI.createVirtualRegister(&AArch64::GPR64RegClass);
6807 SelectTable(I, MRI, 2, AArch64::TBLv8i8Two, AArch64::TBLv16i8Two, false);
6810 SelectTable(I, MRI, 3, AArch64::TBLv8i8Three, AArch64::TBLv16i8Three,
6814 SelectTable(I, MRI, 4, AArch64::TBLv8i8Four, AArch64::TBLv16i8Four, false);
6817 SelectTable(I, MRI, 2, AArch64::TBXv8i8Two, AArch64::TBXv16i8Two, true);
6820 SelectTable(I, MRI, 3, AArch64::TBXv8i8Three, AArch64::TBXv16i8Three, true);
6823 SelectTable(I, MRI, 4, AArch64::TBXv8i8Four, AArch64::TBXv16i8Four, true);
6870 MachineInstr &I, MachineRegisterInfo &MRI) const {
6891 if (!MRI.hasOneDef(Addr))
6895 const MachineInstr *DefMI = &*MRI.def_instr_begin(Addr);
6898 if (!MRI.hasOneDef(OffsetReg))
6900 const MachineInstr &OffsetMI = *MRI.def_instr_begin(OffsetReg);
6905 if (!MRI.hasOneDef(Addr))
6908 DefMI = &*MRI.def_instr_begin(Addr);
6934 std::optional<APInt> AddrDiscVal = getIConstantVRegVal(AddrDisc, MRI);
6951 RBI.constrainGenericRegister(DefReg, AArch64::GPR64RegClass, MRI);
6973 RBI.constrainGenericRegister(DefReg, AArch64::GPR64RegClass, MRI);
6980 MachineRegisterInfo &MRI,
6984 unsigned Opc = MRI.getType(DstReg) == LLT::fixed_vector(8, 8) ? Opc1 : Opc2;
7100 MachineRegisterInfo &MRI = Root.getParent()->getMF()->getRegInfo();
7101 if (MRI.getType(Root.getReg()).getSizeInBits() == 32)
7128 MachineInstr &MI, const MachineRegisterInfo &MRI) const {
7133 MI.getOperand(2).getReg(), MRI)) {
7149 MachineInstr &MI, const MachineRegisterInfo &MRI,
7154 if (MRI.hasOneNonDBGUse(DefReg) ||
7160 if (const auto Worth = isWorthFoldingIntoAddrMode(MI, MRI))
7166 getDefIgnoringCopies(MI.getOperand(2).getReg(), MRI);
7171 if (const auto Worth = isWorthFoldingIntoAddrMode(*OffsetInst, MRI))
7181 return all_of(MRI.use_nodbg_instructions(DefReg),
7203 MachineRegisterInfo &MRI = Root.getParent()->getMF()->getRegInfo();
7204 MachineInstr *OffsetInst = MRI.getVRegDef(Offset.getReg());
7213 OffsetInst = MRI.getVRegDef(OffsetInst->getOperand(1).getReg());
7224 if (!isWorthFoldingIntoExtendedReg(*OffsetInst, MRI, true))
7232 auto ValAndVReg = getIConstantVRegValWithLookThrough(ConstantReg, MRI);
7241 ValAndVReg = getIConstantVRegValWithLookThrough(ConstantReg, MRI);
7273 MachineInstr *ExtInst = getDefIgnoringCopies(OffsetReg, MRI);
7274 auto Ext = getExtendTypeForInst(*ExtInst, MRI, true);
7286 MachineIRBuilder MIB(*MRI.getVRegDef(Root.getReg()));
7315 MachineRegisterInfo &MRI = Root.getParent()->getMF()->getRegInfo();
7330 getOpcodeDef(TargetOpcode::G_PTR_ADD, Root.getReg(), MRI);
7331 if (!PtrAdd || !isWorthFoldingIntoExtendedReg(*PtrAdd, MRI, true))
7337 getDefIgnoringCopies(PtrAdd->getOperand(2).getReg(), MRI);
7354 MachineRegisterInfo &MRI = Root.getParent()->getMF()->getRegInfo();
7357 MachineInstr *Gep = MRI.getVRegDef(Root.getReg());
7364 if (!MRI.hasOneNonDBGUse(Gep->getOperand(0).getReg()))
7387 MachineRegisterInfo &MRI = Root.getParent()->getMF()->getRegInfo();
7391 getOpcodeDef(TargetOpcode::G_PTR_ADD, Root.getReg(), MRI);
7409 getIConstantVRegValWithLookThrough(PtrAdd->getOperand(2).getReg(), MRI);
7461 MachineRegisterInfo &MRI = Root.getParent()->getMF()->getRegInfo();
7464 getOpcodeDef(TargetOpcode::G_PTR_ADD, Root.getReg(), MRI);
7465 if (!PtrAdd || !isWorthFoldingIntoExtendedReg(*PtrAdd, MRI, true))
7470 MachineInstr *OffsetInst = getDefIgnoringCopies(RHS.getReg(), MRI);
7496 if (!isWorthFoldingIntoExtendedReg(*OffsetInst, MRI, true))
7501 getExtendTypeForInst(*OffsetInst, MRI, /*IsLoadStore=*/true);
7528 MachineRegisterInfo &MRI =
7534 if (!isBaseWithConstantOffset(Root, MRI))
7537 MachineInstr *RootDef = MRI.getVRegDef(Root.getReg());
7542 MachineInstr *RHS = MRI.getVRegDef(OffImm.getReg());
7564 MachineRegisterInfo &MRI) const {
7567 MachineInstr &Adrp = *MRI.getVRegDef(RootDef.getOperand(1).getReg());
7602 MachineRegisterInfo &MRI = MF.getRegInfo();
7607 MachineInstr *RootDef = MRI.getVRegDef(Root.getReg());
7618 auto OpFns = tryFoldAddLowIntoImm(*RootDef, Size, MRI);
7623 if (isBaseWithConstantOffset(Root, MRI)) {
7626 MachineInstr *LHSDef = MRI.getVRegDef(LHS.getReg());
7627 MachineInstr *RHSDef = MRI.getVRegDef(RHS.getReg());
7680 MachineRegisterInfo &MRI =
7685 MachineInstr *ShiftInst = MRI.getVRegDef(Root.getReg());
7691 if (!isWorthFoldingIntoExtendedReg(*ShiftInst, MRI, false))
7705 unsigned NumBits = MRI.getType(ShiftReg).getSizeInBits();
7714 MachineInstr &MI, MachineRegisterInfo &MRI, bool IsLoadStore) const {
7721 Size = MRI.getType(MI.getOperand(1).getReg()).getSizeInBits();
7738 unsigned Size = MRI.getType(MI.getOperand(1).getReg()).getSizeInBits();
7775 MachineRegisterInfo &MRI = *MIB.getMRI();
7776 auto Ty = MRI.getType(Reg);
7784 selectCopy(*Copy, TII, MRI, TRI, RBI);
7795 MachineRegisterInfo &MRI =
7801 MachineInstr *RootDef = getDefIgnoringCopies(Root.getReg(), MRI);
7805 if (!isWorthFoldingIntoExtendedReg(*RootDef, MRI, false))
7820 MachineInstr *ExtDef = getDefIgnoringCopies(LHS.getReg(), MRI);
7823 Ext = getExtendTypeForInst(*ExtDef, MRI);
7829 Ext = getExtendTypeForInst(*RootDef, MRI);
7838 if (Ext == AArch64_AM::UXTW && MRI.getType(ExtReg).getSizeInBits() == 32) {
7839 MachineInstr *ExtInst = MRI.getVRegDef(ExtReg);
7860 MachineRegisterInfo &MRI =
7863 auto Extract = getDefSrcRegIgnoringCopies(Root.getReg(), MRI);
7867 getDefSrcRegIgnoringCopies(Extract->MI->getOperand(1).getReg(), MRI);
7878 LLT SrcTy = MRI.getType(Extract->MI->getOperand(1).getReg());
7880 Extract->MI->getOperand(2).getReg(), MRI);
7894 const MachineRegisterInfo &MRI = MI.getParent()->getParent()->getRegInfo();
7898 getIConstantVRegSExtVal(MI.getOperand(0).getReg(), MRI);
7977 const MachineRegisterInfo &MRI = MI.getParent()->getParent()->getRegInfo();
7978 if (MRI.getType(MI.getOperand(0).getReg()).getSizeInBits() != 32)
7999 static void fixupPHIOpBanks(MachineInstr &MI, MachineRegisterInfo &MRI,
8003 const RegisterBank *DstRB = MRI.getRegBankOrNull(DstReg);
8012 const RegisterBank *RB = MRI.getRegBankOrNull(OpReg);
8015 auto *OpDef = MRI.getVRegDef(OpReg);
8016 const LLT &Ty = MRI.getType(OpReg);
8026 MRI.setRegBank(Copy.getReg(0), *DstRB);
8034 MachineRegisterInfo &MRI = MF.getRegInfo();
8069 const LLT &Ty = MRI.getType(MO.getReg());
8074 const RegisterBank *RB = MRI.getRegBankOrNull(MO.getReg());
8086 fixupPHIOpBanks(*MI, MRI, RBI);