Lines Matching defs:MBBI
63 bool expandMI(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
66 MachineBasicBlock::iterator MBBI,
71 MachineBasicBlock::iterator MBBI,
74 bool expandMOVImm(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
78 MachineBasicBlock::iterator MBBI);
79 bool expandCMP_SWAP(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
84 MachineBasicBlock::iterator MBBI,
87 MachineBasicBlock::iterator MBBI,
90 MachineBasicBlock::iterator MBBI, unsigned Opc,
93 MachineBasicBlock::iterator MBBI);
94 bool expandCALL_BTI(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI);
96 MachineBasicBlock::iterator MBBI);
98 MachineBasicBlock::iterator MBBI);
100 MachineBasicBlock::iterator MBBI);
128 MachineBasicBlock::iterator MBBI,
130 MachineInstr &MI = *MBBI;
157 MIBS.push_back(BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(I->Opcode))
165 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(I->Opcode))
178 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(I->Opcode))
189 MIBS.push_back(BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(I->Opcode))
197 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(I->Opcode))
210 MIBS.push_back(BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(I->Opcode))
221 MIBS.push_back(BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(I->Opcode))
238 MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, unsigned LdarOp,
241 MachineInstr &MI = *MBBI;
318 MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
320 MachineInstr &MI = *MBBI;
494 MachineBasicBlock::iterator MBBI) {
618 PRFX = BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(MovPrfxZero))
633 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(LSLZero))
641 PRFX = BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(MovPrfx))
650 DOP = BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(Opcode))
676 finalizeBundle(MBB, PRFX->getIterator(), MBBI->getIterator());
686 MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
688 MachineInstr &MI = *MBBI;
704 BuildMI(MBB, MBBI, DL, TII->get(OpCode1), AddressReg)
711 BuildMI(MBB, MBBI, DL, TII->get(AArch64::MOVi64imm), SizeReg)
763 MachineBasicBlock::iterator MBBI,
776 MachineInstr &MI = *MBBI;
782 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(Opc))
793 // the implicit operands from *MBBI, starting at the regmask.
795 MachineBasicBlock::iterator MBBI,
801 MachineInstr *Call = BuildMI(MBB, MBBI, MBBI->getDebugLoc(), TII->get(Opcode))
808 while (!MBBI->getOperand(RegMaskStartIdx).isRegMask()) {
809 const MachineOperand &MOP = MBBI->getOperand(RegMaskStartIdx);
817 llvm::drop_begin(MBBI->operands(), RegMaskStartIdx))
823 // Create a call to CallTarget, copying over all the operands from *MBBI,
826 MachineBasicBlock::iterator MBBI,
834 return createCallWithOps(MBB, MBBI, TII, Opc, CallTarget, RegMaskStartIdx);
838 MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI) {
844 MachineInstr &MI = *MBBI;
863 OriginalCall = createCallWithOps(MBB, MBBI, TII, AArch64::BLRA, Ops,
867 OriginalCall = createCall(MBB, MBBI, TII, MI.getOperand(1),
872 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(AArch64::ORRXrs))
878 auto *RVCall = BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(AArch64::BL))
892 MachineBasicBlock::iterator MBBI) {
898 MachineInstr &MI = *MBBI;
899 MachineInstr *Call = createCall(MBB, MBBI, TII, MI.getOperand(0),
906 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(AArch64::HINT))
920 MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI) {
921 Register CtxReg = MBBI->getOperand(0).getReg();
922 Register BaseReg = MBBI->getOperand(1).getReg();
923 int Offset = MBBI->getOperand(2).getImm();
924 DebugLoc DL(MBBI->getDebugLoc());
928 BuildMI(MBB, MBBI, DL, TII->get(AArch64::STRXui))
933 MBBI->eraseFromParent();
945 BuildMI(MBB, MBBI, DL, TII->get(Opc), AArch64::X16)
950 BuildMI(MBB, MBBI, DL, TII->get(AArch64::MOVKXi), AArch64::X16)
957 BuildMI(MBB, MBBI, DL, TII->get(AArch64::ORRXrs), AArch64::X17)
962 BuildMI(MBB, MBBI, DL, TII->get(AArch64::PACDB), AArch64::X17)
966 BuildMI(MBB, MBBI, DL, TII->get(AArch64::STRXui))
972 MBBI->eraseFromParent();
978 MachineBasicBlock::iterator MBBI) {
979 MachineInstr &MI = *MBBI;
980 assert((std::next(MBBI) != MBB.end() ||
987 MachineInstrBuilder Cbz = BuildMI(MBB, MBBI, DL, TII->get(AArch64::CBZX))
994 MachineInstr &PrevMI = *std::prev(MBBI);
1020 MachineBasicBlock::iterator MBBI) {
1021 MachineInstr &MI = *MBBI;
1026 // in order to split the block at MBBI.
1027 if (std::next(MBBI) == MBB.end() &&
1087 BuildMI(MBB, MBBI, DL, TII->get(Opc)).addReg(SMReg32).addImm(0);
1093 MachineInstr &PrevMI = *std::prev(MBBI);
1123 MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
1126 MachineInstr &MI = *MBBI;
1139 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(Opc))
1150 MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
1153 MachineInstr &MI = *MBBI;
1165 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(AArch64::ORR_ZZZ))
1175 /// If MBBI references a pseudo instruction that should be expanded here,
1178 MachineBasicBlock::iterator MBBI,
1180 MachineInstr &MI = *MBBI;
1189 return expand_DestructiveOp(MI, MBB, MBBI);
1202 BuildMI(MBB, MBBI, MI.getDebugLoc(),
1211 BuildMI(MBB, MBBI, MI.getDebugLoc(),
1221 BuildMI(MBB, MBBI, MI.getDebugLoc(),
1229 BuildMI(MBB, MBBI, MI.getDebugLoc(),
1237 BuildMI(MBB, MBBI, MI.getDebugLoc(),
1309 MBB.insert(MBBI, NewMI);
1331 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, MI.getDebugLoc(),
1348 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(AArch64::ADRP), DstReg);
1355 MIB2 = BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(AArch64::LDRWui))
1361 MIB2 = BuildMI(MBB, MBBI, DL, TII->get(AArch64::LDRXui))
1404 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(AArch64::ADRP), DstReg)
1406 auto MIB2 = BuildMI(MBB, MBBI, MI.getDebugLoc(),
1426 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(AArch64::ADRP), DstReg)
1440 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(AArch64::MOVKXi), DstReg)
1447 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(AArch64::ADDXri))
1459 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(AArch64::ADDXri))
1479 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(AArch64::MRS), DstReg)
1486 return expandMOVImm(MBB, MBBI, 32);
1488 return expandMOVImm(MBB, MBBI, 64);
1496 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(AArch64::RET))
1503 return expandCMP_SWAP(MBB, MBBI, AArch64::LDAXRB, AArch64::STLXRB,
1508 return expandCMP_SWAP(MBB, MBBI, AArch64::LDAXRH, AArch64::STLXRH,
1513 return expandCMP_SWAP(MBB, MBBI, AArch64::LDAXRW, AArch64::STLXRW,
1518 return expandCMP_SWAP(MBB, MBBI,
1526 return expandCMP_SWAP_128(MBB, MBBI, NextMBBI);
1531 BuildMI(MBB, MBBI, MI.getDebugLoc(),
1562 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(AArch64::IRG))
1571 BuildMI(MBB, MBBI, MI.getDebugLoc(),
1582 return expandSetTagLoop(MBB, MBBI, NextMBBI);
1589 return expandSVESpillFill(MBB, MBBI, AArch64::STR_ZXI, 4);
1591 return expandSVESpillFill(MBB, MBBI, AArch64::STR_ZXI, 3);
1593 return expandSVESpillFill(MBB, MBBI, AArch64::STR_ZXI, 2);
1595 return expandSVESpillFill(MBB, MBBI, AArch64::STR_PXI, 2);
1597 return expandSVESpillFill(MBB, MBBI, AArch64::LDR_ZXI, 4);
1599 return expandSVESpillFill(MBB, MBBI, AArch64::LDR_ZXI, 3);
1601 return expandSVESpillFill(MBB, MBBI, AArch64::LDR_ZXI, 2);
1603 return expandSVESpillFill(MBB, MBBI, AArch64::LDR_PXI, 2);
1606 return expandCALL_RVMARKER(MBB, MBBI);
1608 return expandCALL_BTI(MBB, MBBI);
1610 return expandStoreSwiftAsyncContext(MBB, MBBI);
1612 auto *NewMBB = expandRestoreZA(MBB, MBBI);
1618 auto *NewMBB = expandCondSMToggle(MBB, MBBI);
1631 MBB, MBBI, AArch64::ZPR2RegClass, AArch64::ZPR2StridedRegClass,
1635 MBB, MBBI, AArch64::ZPR2RegClass, AArch64::ZPR2StridedRegClass,
1639 MBB, MBBI, AArch64::ZPR2RegClass, AArch64::ZPR2StridedRegClass,
1643 MBB, MBBI, AArch64::ZPR2RegClass, AArch64::ZPR2StridedRegClass,
1647 MBB, MBBI, AArch64::ZPR2RegClass, AArch64::ZPR2StridedRegClass,
1651 MBB, MBBI, AArch64::ZPR2RegClass, AArch64::ZPR2StridedRegClass,
1655 MBB, MBBI, AArch64::ZPR2RegClass, AArch64::ZPR2StridedRegClass,
1659 MBB, MBBI, AArch64::ZPR2RegClass, AArch64::ZPR2StridedRegClass,
1662 return expandMultiVecPseudo(MBB, MBBI, AArch64::ZPR2RegClass,
1666 return expandMultiVecPseudo(MBB, MBBI, AArch64::ZPR2RegClass,
1670 return expandMultiVecPseudo(MBB, MBBI, AArch64::ZPR2RegClass,
1674 return expandMultiVecPseudo(MBB, MBBI, AArch64::ZPR2RegClass,
1679 MBB, MBBI, AArch64::ZPR2RegClass, AArch64::ZPR2StridedRegClass,
1683 MBB, MBBI, AArch64::ZPR2RegClass, AArch64::ZPR2StridedRegClass,
1687 MBB, MBBI, AArch64::ZPR2RegClass, AArch64::ZPR2StridedRegClass,
1691 MBB, MBBI, AArch64::ZPR2RegClass, AArch64::ZPR2StridedRegClass,
1695 MBB, MBBI, AArch64::ZPR4RegClass, AArch64::ZPR4StridedRegClass,
1699 MBB, MBBI, AArch64::ZPR4RegClass, AArch64::ZPR4StridedRegClass,
1703 MBB, MBBI, AArch64::ZPR4RegClass, AArch64::ZPR4StridedRegClass,
1707 MBB, MBBI, AArch64::ZPR4RegClass, AArch64::ZPR4StridedRegClass,
1711 MBB, MBBI, AArch64::ZPR4RegClass, AArch64::ZPR4StridedRegClass,
1715 MBB, MBBI, AArch64::ZPR4RegClass, AArch64::ZPR4StridedRegClass,
1719 MBB, MBBI, AArch64::ZPR4RegClass, AArch64::ZPR4StridedRegClass,
1723 MBB, MBBI, AArch64::ZPR4RegClass, AArch64::ZPR4StridedRegClass,
1726 return expandMultiVecPseudo(MBB, MBBI, AArch64::ZPR4RegClass,
1730 return expandMultiVecPseudo(MBB, MBBI, AArch64::ZPR4RegClass,
1734 return expandMultiVecPseudo(MBB, MBBI, AArch64::ZPR4RegClass,
1738 return expandMultiVecPseudo(MBB, MBBI, AArch64::ZPR4RegClass,
1743 MBB, MBBI, AArch64::ZPR4RegClass, AArch64::ZPR4StridedRegClass,
1747 MBB, MBBI, AArch64::ZPR4RegClass, AArch64::ZPR4StridedRegClass,
1751 MBB, MBBI, AArch64::ZPR4RegClass, AArch64::ZPR4StridedRegClass,
1755 MBB, MBBI, AArch64::ZPR4RegClass, AArch64::ZPR4StridedRegClass,
1758 return expandFormTuplePseudo(MBB, MBBI, NextMBBI, 2);
1760 return expandFormTuplePseudo(MBB, MBBI, NextMBBI, 4);
1770 MachineBasicBlock::iterator MBBI = MBB.begin(), E = MBB.end();
1771 while (MBBI != E) {
1772 MachineBasicBlock::iterator NMBBI = std::next(MBBI);
1773 Modified |= expandMI(MBB, MBBI, NMBBI);
1774 MBBI = NMBBI;