Lines Matching defs:LogicOpcode

5907   unsigned LogicOpcode = N->getOpcode();
5909   assert(ISD::isBitwiseLogicOp(LogicOpcode) && "Expected logic opcode");
5937         !TLI.isOperationLegalOrCustom(LogicOpcode, XVT))
5943         LegalTypes && !TLI.isTypeDesirableForOp(LogicOpcode, XVT))
5946     SDValue Logic = DAG.getNode(LogicOpcode, DL, XVT, X, Y);
5962     if (LegalOperations && !TLI.isOperationLegal(LogicOpcode, XVT))
5970     SDValue Logic = DAG.getNode(LogicOpcode, DL, XVT, X, Y);
5982     SDValue Logic = DAG.getNode(LogicOpcode, DL, XVT, X, Y);
5991     SDValue Logic = DAG.getNode(LogicOpcode, DL, XVT, X, Y);
6005     SDValue Logic0 = DAG.getNode(LogicOpcode, DL, VT, X, Y);
6006     SDValue Logic1 = DAG.getNode(LogicOpcode, DL, VT, X1, Y1);
6023       SDValue Logic = DAG.getNode(LogicOpcode, DL, XVT, X, Y);
6057     if (LogicOpcode == ISD::XOR && !ShOp.isUndef())
6062       SDValue Logic = DAG.getNode(LogicOpcode, DL, VT,
6070     if (LogicOpcode == ISD::XOR && !ShOp.isUndef())
6075       SDValue Logic = DAG.getNode(LogicOpcode, DL, VT, N0.getOperand(1),
7007   unsigned LogicOpcode = N->getOpcode();
7008   assert(ISD::isBitwiseLogicOp(LogicOpcode) &&
7016   if (LogicOp.getOpcode() != LogicOpcode ||
7042   SDValue LogicX = DAG.getNode(LogicOpcode, DL, VT, X0, X1);
7044   return DAG.getNode(LogicOpcode, DL, VT, NewShift, Z);
7055   unsigned LogicOpcode = N->getOpcode();
7056   assert(ISD::isBitwiseLogicOp(LogicOpcode) &&
7058   if (LeftHand.getOpcode() != LogicOpcode ||
7059       RightHand.getOpcode() != LogicOpcode)
7081   return DAG.getNode(LogicOpcode, DL, VT, CombinedShifts, W);
9796   unsigned LogicOpcode = LogicOp.getOpcode();
9797   if (LogicOpcode != ISD::AND && LogicOpcode != ISD::OR &&
9798       LogicOpcode != ISD::XOR)
9856   return DAG.getNode(LogicOpcode, DL, VT, NewShift1, NewShift2,