Lines Matching defs:vi1

12 void test_builtin_reduce_max(float4 vf1, si8 vi1, u4 vu1) {
18   // CHECK:      [[VI1:%.+]] = load <8 x i16>, ptr %vi1.addr, align 16
20   short r2 = __builtin_reduce_max(vi1);
34   const si8 cvi1 = vi1;
38 void test_builtin_reduce_min(float4 vf1, si8 vi1, u4 vu1) {
44   // CHECK:      [[VI1:%.+]] = load <8 x i16>, ptr %vi1.addr, align 16
46   short r2 = __builtin_reduce_min(vi1);
60   const si8 cvi1 = vi1;
64 void test_builtin_reduce_add(si8 vi1, u4 vu1) {
65   // CHECK:      [[VI1:%.+]] = load <8 x i16>, ptr %vi1.addr, align 16
67   short r2 = __builtin_reduce_add(vi1);
76   const si8 cvi1 = vi1;
86 void test_builtin_reduce_mul(si8 vi1, u4 vu1) {
87   // CHECK:      [[VI1:%.+]] = load <8 x i16>, ptr %vi1.addr, align 16
89   short r2 = __builtin_reduce_mul(vi1);
98   const si8 cvi1 = vi1;
108 void test_builtin_reduce_xor(si8 vi1, u4 vu1) {
110   // CHECK:      [[VI1:%.+]] = load <8 x i16>, ptr %vi1.addr, align 16
112   short r2 = __builtin_reduce_xor(vi1);
119 void test_builtin_reduce_or(si8 vi1, u4 vu1) {
121   // CHECK:      [[VI1:%.+]] = load <8 x i16>, ptr %vi1.addr, align 16
123   short r2 = __builtin_reduce_or(vi1);
130 void test_builtin_reduce_and(si8 vi1, u4 vu1) {
132   // CHECK:      [[VI1:%.+]] = load <8 x i16>, ptr %vi1.addr, align 16
134   short r2 = __builtin_reduce_and(vi1);