Lines Matching refs:Features

262     llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, StringRef CPU,
268     Features["64bit"] = true;
271     Features["32bit"] = true;
288   return TargetInfo::initFeatureMap(Features, Diags, CPU, AllFeatures);
331 bool RISCVTargetInfo::handleTargetFeatures(std::vector<std::string> &Features,
334   auto ParseResult = llvm::RISCVISAInfo::parseFeatures(XLen, Features);
354       llvm::is_contained(Features, "+unaligned-scalar-mem");
356   if (llvm::is_contained(Features, "+experimental"))
389 static void populateNegativeRISCVFeatures(std::vector<std::string> &Features) {
398   Features.insert(Features.end(), FeatStrings.begin(), FeatStrings.end());
402                                  std::vector<std::string> &Features) {
407     Features.push_back(FullArchStr.str());
411     populateNegativeRISCVFeatures(Features);
414     Features.insert(Features.end(), FeatStrings.begin(), FeatStrings.end());
418 ParsedTargetAttr RISCVTargetInfo::parseTargetAttr(StringRef Features) const {
420   if (Features == "default")
423   Features.split(AttrFeatures, ";");
427                                 std::vector<std::string> &Features) {
438         Features.push_back(Ext.front() + TargetFeature);
440         Features.push_back(Ext.str());
450       Ret.Features.clear();
457         handleArchExtension(AttrString, Ret.Features);
460         handleFullArchString(AttrString, Ret.Features);
469         // Update Features with CPU's features
472           Ret.Features.clear();
473           handleFullArchString(MarchFromCPU, Ret.Features);
486       handleArchExtension(Feature, Ret.Features);
492 uint64_t RISCVTargetInfo::getFMVPriority(ArrayRef<StringRef> Features) const {
496   for (StringRef Feature : Features) {