Lines Matching full:for

18  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
47 #define MCS7840_DEV_REG_SP1 0x00 /* Options for UART 1, R/W */
48 #define MCS7840_DEV_REG_CONTROL1 0x01 /* Control bits for UART 1,
58 #define MCS7840_DEV_REG_SP2 0x08 /* Options for UART 2, R/W */
59 #define MCS7840_DEV_REG_CONTROL2 0x09 /* Control bits for UART 2,
61 #define MCS7840_DEV_REG_SP3 0x0a /* Options for UART 3, R/W */
62 #define MCS7840_DEV_REG_CONTROL3 0x0b /* Control bits for UART 3,
64 #define MCS7840_DEV_REG_SP4 0x0c /* Options for UART 4, R/W */
65 #define MCS7840_DEV_REG_CONTROL4 0x0d /* Control bits for UART 4,
67 #define MCS7840_DEV_REG_PLL_DIV_M 0x0e /* Pre-diviedr for PLL, R/W */
69 #define MCS7840_DEV_REG_PLL_DIV_N 0x10 /* Loop divider for PLL, R/W */
73 #define MCS7840_DEV_REG_CLOCK_SELECT12 0x13 /* Clock source for ports 1 &
75 #define MCS7840_DEV_REG_CLOCK_SELECT34 0x14 /* Clock source for ports 3 &
94 * configuration for Port 1,
97 * configuration for Port 2,
100 * configuration for Port 3,
103 * configuration for Port 4,
105 #define MCS7840_DEV_REG_RX_SAMPLING12 0x30 /* RX sampling for ports 1 &
107 #define MCS7840_DEV_REG_RX_SAMPLING34 0x31 /* RX sampling for ports 3 &
109 #define MCS7840_DEV_REG_BI_FIFO_STAT1 0x32 /* Bulk-In FIFO Stat for Port
112 #define MCS7840_DEV_REG_BO_FIFO_STAT1 0x33 /* Bulk-out FIFO Stat for Port
115 #define MCS7840_DEV_REG_BI_FIFO_STAT2 0x34 /* Bulk-In FIFO Stat for Port
118 #define MCS7840_DEV_REG_BO_FIFO_STAT2 0x35 /* Bulk-out FIFO Stat for Port
121 #define MCS7840_DEV_REG_BI_FIFO_STAT3 0x36 /* Bulk-In FIFO Stat for Port
124 #define MCS7840_DEV_REG_BO_FIFO_STAT3 0x37 /* Bulk-out FIFO Stat for Port
127 #define MCS7840_DEV_REG_BI_FIFO_STAT4 0x38 /* Bulk-In FIFO Stat for Port
130 #define MCS7840_DEV_REG_BO_FIFO_STAT4 0x39 /* Bulk-out FIFO Stat for Port
134 * frames for Port 1, R/W */
136 * frames for Port 1, R/W */
138 * frames for Port 1, R/W */
140 * frames for Port 1, R/W */
144 * value for Bulk-Out for Port
147 * value for Bulk-Out and
148 * enable flag for Port 1, R/W */
150 * value for Bulk-Out for Port
153 * value for Bulk-Out and
154 * enable flag for Port 2, R/W */
156 * value for Bulk-Out for Port
159 * value for Bulk-Out and
160 * enable flag for Port 3, R/W */
162 * value for Bulk-Out for Port
165 * value for Bulk-Out and
166 * enable flag for Port 4, R/W */
168 /* Bits for SPx registers */
198 /* Bits for CONTROLx registers */
208 #define MCS7840_DEV_CONTROLx_UNUSED2 0x08 /* Reserved for ports
215 * works for IrDA mode
218 * works only for
223 * works for IrDA mode
228 * Bits for PINPONGx registers
230 * for Bulk-In FIFOs are swapped. One of buffers is used
231 * for USB trnasfer, other for receiving data from UART.
241 * confirms, that it is register for GPIO_0 and GPIO_1 data input/output.
243 * authors as "number of port" indicator, grounded (0) for two-port
244 * devices and pulled-up to 1 for 4-port devices.
252 * Constants for PLL dividers
257 #define MCS7840_DEV_PLL_DIV_M_BITS 6 /* Number of useful bits for M
259 #define MCS7840_DEV_PLL_DIV_M_MASK 0x3f /* Mask for M divider */
260 #define MCS7840_DEV_PLL_DIV_M_MIN 1 /* Minimum value for M, 0 is
262 #define MCS7840_DEV_PLL_DIV_M_DEF 1 /* Default value for M */
263 #define MCS7840_DEV_PLL_DIV_M_MAX 63 /* Maximum value for M */
264 #define MCS7840_DEV_PLL_DIV_N_BITS 6 /* Number of useful bits for N
266 #define MCS7840_DEV_PLL_DIV_N_MASK 0x3f /* Mask for N divider */
267 #define MCS7840_DEV_PLL_DIV_N_MIN 1 /* Minimum value for N, 0 is
269 #define MCS7840_DEV_PLL_DIV_N_DEF 8 /* Default value for N */
270 #define MCS7840_DEV_PLL_DIV_N_MAX 63 /* Maximum value for N */
272 /* Bits for CLOCK_MUX register */
292 /* Bits for CLOCK_SELECTxx registers */
293 #define MCS7840_DEV_CLOCK_SELECT1_MASK 0x07 /* Bits for port 1 in
295 #define MCS7840_DEV_CLOCK_SELECT1_SHIFT 0 /* Shift for port 1in
297 #define MCS7840_DEV_CLOCK_SELECT2_MASK 0x38 /* Bits for port 2 in
299 #define MCS7840_DEV_CLOCK_SELECT2_SHIFT 3 /* Shift for port 2 in
301 #define MCS7840_DEV_CLOCK_SELECT3_MASK 0x07 /* Bits for port 3 in
303 #define MCS7840_DEV_CLOCK_SELECT3_SHIFT 0 /* Shift for port 3 in
305 #define MCS7840_DEV_CLOCK_SELECT4_MASK 0x38 /* Bits for port 4 in
307 #define MCS7840_DEV_CLOCK_SELECT4_SHIFT 3 /* Shift for port 4 in
310 * from 96Mhz, default for all
315 #define MCS7840_DEV_CLOCK_SELECT_PLL 0x04 /* PLL output (see for M and N
322 /* Bits for MODE register */
342 /* Bits for SPx ICG */
348 * Bits for RX_SAMPLINGxx registers
353 #define MCS7840_DEV_RX_SAMPLING1_MASK 0x0f /* Bits for port 1 in
355 #define MCS7840_DEV_RX_SAMPLING1_SHIFT 0 /* Shift for port 1in
357 #define MCS7840_DEV_RX_SAMPLING2_MASK 0xf0 /* Bits for port 2 in
359 #define MCS7840_DEV_RX_SAMPLING2_SHIFT 4 /* Shift for port 2 in
361 #define MCS7840_DEV_RX_SAMPLING3_MASK 0x0f /* Bits for port 3 in
363 #define MCS7840_DEV_RX_SAMPLING3_SHIFT 0 /* Shift for port 3 in
365 #define MCS7840_DEV_RX_SAMPLING4_MASK 0xf0 /* Bits for port 4 in
367 #define MCS7840_DEV_RX_SAMPLING4_SHIFT 4 /* Shift for port 4 in
369 #define MCS7840_DEV_RX_SAMPLINGx_MIN 0 /* Max for any RX Sampling */
370 #define MCS7840_DEV_RX_SAMPLINGx_DEF 7 /* Default for any RX
372 #define MCS7840_DEV_RX_SAMPLINGx_MAX 15 /* Min for any RX Sampling */
374 /* Bits for ZERO_PERIODx */
379 /* Bits for ZERO_ENABLE */
381 * zero-sized replies for port
384 * zero-sized replies for port
387 * zero-sized replies for port
390 * zero-sized replies for port
393 /* Bits for THR_VAL_HIGHx */
400 #define MCS7840_DEV_REG_DCR0_1 0x04 /* Device contol register 0 for Port
402 #define MCS7840_DEV_REG_DCR1_1 0x05 /* Device contol register 1 for Port
404 #define MCS7840_DEV_REG_DCR2_1 0x06 /* Device contol register 2 for Port
406 #define MCS7840_DEV_REG_DCR0_2 0x16 /* Device contol register 0 for Port
408 #define MCS7840_DEV_REG_DCR1_2 0x17 /* Device contol register 1 for Port
410 #define MCS7840_DEV_REG_DCR2_2 0x18 /* Device contol register 2 for Port
412 #define MCS7840_DEV_REG_DCR0_3 0x19 /* Device contol register 0 for Port
414 #define MCS7840_DEV_REG_DCR1_3 0x1a /* Device contol register 1 for Port
416 #define MCS7840_DEV_REG_DCR2_3 0x1b /* Device contol register 2 for Port
418 #define MCS7840_DEV_REG_DCR0_4 0x1c /* Device contol register 0 for Port
420 #define MCS7840_DEV_REG_DCR1_4 0x1d /* Device contol register 1 for Port
422 #define MCS7840_DEV_REG_DCR2_4 0x1e /* Device contol register 2 for Port
431 * ONLY FOR PORT 1 */
434 * FOR PORT 1 */
437 * FOR PORT 1 */
450 * ONLY FOR PORT 1 */
452 * 6mA, WORKS ONLY FOR
456 * ONLY FOR PORT 1 */
458 * 10mA, WORKS ONLY FOR
461 * 12mA, WORKS ONLY FOR
477 * WORKS ONLY FOR PORT 1 */
481 * WORKS ONLY FOR PORT 1 */
510 * Thesse can be calculated as "1 << portnumber" for Bulk-out and
511 * "1 << (portnumber+1)" for Bulk-in
573 #define MCS7840_UART_LCR_DATALENMASK 0x03 /* Mask for data length */
579 #define MCS7840_UART_LCR_STOPBMASK 0x04 /* Mask for stop bits */
584 #define MCS7840_UART_LCR_PARITYMASK 0x38 /* Mask for all parity data */
596 #define MCS7840_UART_LSR_RHRAVAIL 0x01 /* Data available for read */
602 * ready for transmit */