Lines Matching defs:ProcModel

105   unsigned EmitRegisterFileTables(const CodeGenProcModel &ProcModel,
107   void EmitLoadStoreQueueInfo(const CodeGenProcModel &ProcModel,
109   void EmitExtraProcessorInfo(const CodeGenProcModel &ProcModel,
113   void EmitProcessorResourceSubUnits(const CodeGenProcModel &ProcModel,
115   void EmitProcessorResources(const CodeGenProcModel &ProcModel,
118                              const CodeGenProcModel &ProcModel);
120                           const CodeGenProcModel &ProcModel);
123                            const CodeGenProcModel &ProcModel);
124   void GenSchedClassTables(const CodeGenProcModel &ProcModel,
444   for (const CodeGenProcModel &ProcModel : SchedModels.procModels()) {
446     if (!ItinsDefSet.insert(ProcModel.ItinsDef).second)
449     RecVec FUs = ProcModel.ItinsDef->getValueAsListOfDefs("FU");
453     StringRef Name = ProcModel.ItinsDef->getName();
463     RecVec BPs = ProcModel.ItinsDef->getValueAsListOfDefs("BP");
498   for (const CodeGenProcModel &ProcModel : SchedModels.procModels()) {
504     if (!ProcModel.hasItineraries())
507     StringRef Name = ProcModel.ItinsDef->getName();
510     assert(ProcModel.ItinDefList.size() == ItinList.size() && "bad Itins");
516       Record *ItinData = ProcModel.ItinDefList[SchedClassIdx];
678     const CodeGenProcModel &ProcModel, raw_ostream &OS) {
679   OS << "\nstatic const unsigned " << ProcModel.ModelName
683   for (unsigned i = 0, e = ProcModel.ProcResourceDefs.size(); i < e; ++i) {
684     Record *PRDef = ProcModel.ProcResourceDefs[i];
690           SchedModels.findProcResUnits(RUDef, ProcModel, PRDef->getLoc());
692         OS << "  " << ProcModel.getProcResourceIdx(RU) << ", ";
700 static void EmitRetireControlUnitInfo(const CodeGenProcModel &ProcModel,
703   if (Record *RCU = ProcModel.RetireControlUnit) {
714 static void EmitRegisterFileInfo(const CodeGenProcModel &ProcModel,
718     OS << ProcModel.ModelName << "RegisterFiles,\n  " << (1 + NumRegisterFiles);
724     OS << ProcModel.ModelName << "RegisterCosts,\n  ";
731 SubtargetEmitter::EmitRegisterFileTables(const CodeGenProcModel &ProcModel,
733   if (llvm::all_of(ProcModel.RegisterFiles, [](const CodeGenRegisterFile &RF) {
740   OS << "static const llvm::MCRegisterCostEntry " << ProcModel.ModelName
744   for (const CodeGenRegisterFile &RF : ProcModel.RegisterFiles) {
763   OS << "static const llvm::MCRegisterFileDesc " << ProcModel.ModelName
769   for (const CodeGenRegisterFile &RD : ProcModel.RegisterFiles) {
783 void SubtargetEmitter::EmitLoadStoreQueueInfo(const CodeGenProcModel &ProcModel,
786   if (ProcModel.LoadQueue) {
787     const Record *Queue = ProcModel.LoadQueue->getValueAsDef("QueueDescriptor");
788     QueueID = 1 + std::distance(ProcModel.ProcResourceDefs.begin(),
789                                 find(ProcModel.ProcResourceDefs, Queue));
794   if (ProcModel.StoreQueue) {
796         ProcModel.StoreQueue->getValueAsDef("QueueDescriptor");
797     QueueID = 1 + std::distance(ProcModel.ProcResourceDefs.begin(),
798                                 find(ProcModel.ProcResourceDefs, Queue));
803 void SubtargetEmitter::EmitExtraProcessorInfo(const CodeGenProcModel &ProcModel,
807   unsigned NumCostEntries = EmitRegisterFileTables(ProcModel, OS);
810   OS << "\nstatic const llvm::MCExtraProcessorInfo " << ProcModel.ModelName
814   EmitRetireControlUnitInfo(ProcModel, OS);
818   EmitRegisterFileInfo(ProcModel, ProcModel.RegisterFiles.size(),
822   EmitLoadStoreQueueInfo(ProcModel, OS);
827 void SubtargetEmitter::EmitProcessorResources(const CodeGenProcModel &ProcModel,
829   EmitProcessorResourceSubUnits(ProcModel, OS);
832   OS << "static const llvm::MCProcResourceDesc " << ProcModel.ModelName
838   for (unsigned i = 0, e = ProcModel.ProcResourceDefs.size(); i < e; ++i) {
839     Record *PRDef = ProcModel.ProcResourceDefs[i];
856                                                 ProcModel, PRDef->getLoc());
857         SuperIdx = ProcModel.getProcResourceIdx(SuperDef);
867       OS << ProcModel.ModelName << "ProcResourceSubUnits + "
884                                      const CodeGenProcModel &ProcModel) {
897       if (&SchedModels.getProcModel(ModelDef) != &ProcModel)
904                           ProcModel.ModelName +
913   for (Record *WR : ProcModel.WriteResDefs) {
921                                           ProcModel.ModelName);
931   // TODO: If ProcModel has a base model (previous generation processor),
934     PrintFatalError(ProcModel.ModelDef->getLoc(),
944                                           const CodeGenProcModel &ProcModel) {
956       if (&SchedModels.getProcModel(ModelDef) != &ProcModel)
963                           ProcModel.ModelName +
972   for (Record *RA : ProcModel.ReadAdvanceDefs) {
980                                           ProcModel.ModelName);
990   // TODO: If ProcModel has a base model (previous generation processor),
993     PrintFatalError(ProcModel.ModelDef->getLoc(),
1050 void SubtargetEmitter::GenSchedClassTables(const CodeGenProcModel &ProcModel,
1054   if (!ProcModel.hasInstrSchedModel())
1075       if (CGT.ProcIndex == ProcModel.Index) {
1090       if (!is_contained(SC.ProcIndices, ProcModel.Index))
1101         if (&ProcModel == &SchedModels.getProcModel(RWModelDef)) {
1115       for (Record *I : ProcModel.ItinRWDefs) {
1124         LLVM_DEBUG(dbgs() << ProcModel.ModelName
1137       SchedModels.expandRWSeqForProc(W, WriteSeq, /*IsRead=*/false, ProcModel);
1146       if (!ProcModel.hasReadOfWrite(SchedModels.getSchedWrite(WriteID).TheDef))
1153             FindWriteResources(SchedModels.getSchedWrite(WS), ProcModel);
1215         ExpandProcResources(PRVec, ReleaseAtCycles, AcquireAtCycles, ProcModel);
1221           WPREntry.ProcResourceIdx = ProcModel.getProcResourceIdx(PRVec[PRIdx]);
1269           FindReadAdvance(SchedModels.getSchedRead(Reads[UseIdx]), ProcModel);
1541   for (const CodeGenProcModel &ProcModel : SchedModels.procModels()) {
1542     GenSchedClassTables(ProcModel, SchedTables);