Lines Matching defs:EnumValue

129     OS << "  " << Reg.getName() << " = " << Reg.EnumValue << ",\n";
130   assert(Registers.size() == Registers.back().EnumValue &&
149       OS << "  " << RC.getIdName() << " = " << RC.EnumValue << ",\n";
619   OS << Idx->EnumValue;
653     unsigned Cur = (*I)->EnumValue;
672     CodeGenSubRegIndex *&Entry = Vec[I.first->EnumValue - 1];
679     auto *&Entry = Vec[I.first->EnumValue - 1];
680     assert((!Entry || Entry == I.second) && "Expected EnumValue to be unique");
906     diffEncode(SubRegLists[i], Reg.EnumValue, SR.begin(), SR.end());
917     diffEncode(SuperRegLists[i], Reg.EnumValue, SuperRegList.begin(),
1029         BVE.add(Target.getRegBank().getReg(Reg)->EnumValue);
1282         assert(RC.EnumValue == EV && "Unexpected order of register classes");
1332       IdxList &SRIList = SuperRegIdxLists[RC.EnumValue];
1408          << SuperRegIdxSeqs.get(SuperRegIdxLists[RC.EnumValue]) << ",\n    ";
1460       InAllocClass.set(Reg.EnumValue);
1515           OS << "      " << SRC->EnumValue + 1 << ",\t// " << Idx.getName()
1550         unsigned EnumValue = 0;
1553           EnumValue = SubRegClass->EnumValue + 1;
1556         OS << "      " << EnumValue << ",\t// " << RC.getName() << ':'
1594           return std::pair(*LHS->getBaseClassOrder(), LHS->EnumValue) <
1595                  std::pair(*RHS->getBaseClassOrder(), RHS->EnumValue);
1854       if (!SubClasses.test(SRC.EnumValue))