Lines Matching full:arm
1 //===-- ARMTargetParser - Parser for ARM target features --------*- C++ -*-===//
9 // This file implements a target parser to recognise ARM hardware features
26 .Case("thumb,arm", "arm,thumb")
31 ARM::ArchKind ARM::parseArch(StringRef Arch) {
42 unsigned ARM::parseArchVersion(StringRef Arch) {
97 static ARM::ProfileKind getProfileKind(ARM::ArchKind AK) {
99 case ARM::ArchKind::ARMV6M:
100 case ARM::ArchKind::ARMV7M:
101 case ARM::ArchKind::ARMV7EM:
102 case ARM::ArchKind::ARMV8MMainline:
103 case ARM::ArchKind::ARMV8MBaseline:
104 case ARM::ArchKind::ARMV8_1MMainline:
105 return ARM::ProfileKind::M;
106 case ARM::ArchKind::ARMV7R:
107 case ARM::ArchKind::ARMV8R:
108 return ARM::ProfileKind::R;
109 case ARM::ArchKind::ARMV7A:
110 case ARM::ArchKind::ARMV7VE:
111 case ARM::ArchKind::ARMV7K:
112 case ARM::ArchKind::ARMV8A:
113 case ARM::ArchKind::ARMV8_1A:
114 case ARM::ArchKind::ARMV8_2A:
115 case ARM::ArchKind::ARMV8_3A:
116 case ARM::ArchKind::ARMV8_4A:
117 case ARM::ArchKind::ARMV8_5A:
118 case ARM::ArchKind::ARMV8_6A:
119 case ARM::ArchKind::ARMV8_7A:
120 case ARM::ArchKind::ARMV8_8A:
121 case ARM::ArchKind::ARMV8_9A:
122 case ARM::ArchKind::ARMV9A:
123 case ARM::ArchKind::ARMV9_1A:
124 case ARM::ArchKind::ARMV9_2A:
125 case ARM::ArchKind::ARMV9_3A:
126 case ARM::ArchKind::ARMV9_4A:
127 case ARM::ArchKind::ARMV9_5A:
128 return ARM::ProfileKind::A;
129 case ARM::ArchKind::ARMV4:
130 case ARM::ArchKind::ARMV4T:
131 case ARM::ArchKind::ARMV5T:
132 case ARM::ArchKind::ARMV5TE:
133 case ARM::ArchKind::ARMV5TEJ:
134 case ARM::ArchKind::ARMV6:
135 case ARM::ArchKind::ARMV6K:
136 case ARM::ArchKind::ARMV6T2:
137 case ARM::ArchKind::ARMV6KZ:
138 case ARM::ArchKind::ARMV7S:
139 case ARM::ArchKind::IWMMXT:
140 case ARM::ArchKind::IWMMXT2:
141 case ARM::ArchKind::XSCALE:
142 case ARM::ArchKind::INVALID:
143 return ARM::ProfileKind::INVALID;
149 ARM::ProfileKind ARM::parseArchProfile(StringRef Arch) {
154 bool ARM::getFPUFeatures(ARM::FPUKind FPUKind,
219 ARM::FPUKind ARM::parseFPU(StringRef FPU) {
228 ARM::NeonSupportLevel ARM::getFPUNeonSupportLevel(ARM::FPUKind FPUKind) {
234 StringRef ARM::getFPUSynonym(StringRef FPU) {
251 StringRef ARM::getFPUName(ARM::FPUKind FPUKind) {
257 ARM::FPUVersion ARM::getFPUVersion(ARM::FPUKind FPUKind) {
263 ARM::FPURestriction ARM::getFPURestriction(ARM::FPUKind FPUKind) {
269 ARM::FPUKind ARM::getDefaultFPU(StringRef CPU, ARM::ArchKind AK) {
271 return ARM::ARMArchNames[static_cast<unsigned>(AK)].DefaultFPU;
273 return StringSwitch<ARM::FPUKind>(CPU)
277 .Default(ARM::FK_INVALID);
280 uint64_t ARM::getDefaultExtensions(StringRef CPU, ARM::ArchKind AK) {
282 return ARM::ARMArchNames[static_cast<unsigned>(AK)].ArchBaseExtensions;
290 .Default(ARM::AEK_INVALID);
293 bool ARM::getHWDivFeatures(uint64_t HWDivKind,
300 Features.push_back("+hwdiv-arm");
302 Features.push_back("-hwdiv-arm");
312 bool ARM::getExtensionFeatures(uint64_t Extensions,
328 StringRef ARM::getArchName(ARM::ArchKind AK) {
332 StringRef ARM::getCPUAttr(ARM::ArchKind AK) {
336 StringRef ARM::getSubArch(ARM::ArchKind AK) {
340 unsigned ARM::getArchAttr(ARM::ArchKind AK) {
344 StringRef ARM::getArchExtName(uint64_t ArchExtKind) {
356 StringRef ARM::getArchExtFeature(StringRef ArchExt) {
366 static ARM::FPUKind findDoublePrecisionFPU(ARM::FPUKind InputFPUKind) {
367 if (InputFPUKind == ARM::FK_INVALID || InputFPUKind == ARM::FK_NONE)
368 return ARM::FK_INVALID;
370 const ARM::FPUName &InputFPU = ARM::FPUNames[InputFPUKind];
374 if (ARM::isDoublePrecision(InputFPU.Restriction))
379 for (const ARM::FPUName &CandidateFPU : ARM::FPUNames) {
382 ARM::has32Regs(CandidateFPU.Restriction) ==
383 ARM::has32Regs(InputFPU.Restriction) &&
384 ARM::isDoublePrecision(CandidateFPU.Restriction)) {
390 return ARM::FK_INVALID;
393 static ARM::FPUKind findSinglePrecisionFPU(ARM::FPUKind InputFPUKind) {
394 if (InputFPUKind == ARM::FK_INVALID || InputFPUKind == ARM::FK_NONE)
395 return ARM::FK_INVALID;
397 const ARM::FPUName &InputFPU = ARM::FPUNames[InputFPUKind];
401 if (!ARM::isDoublePrecision(InputFPU.Restriction))
406 for (const ARM::FPUName &CandidateFPU : ARM::FPUNames) {
409 ARM::has32Regs(CandidateFPU.Restriction) ==
410 ARM::has32Regs(InputFPU.Restriction) &&
411 !ARM::isDoublePrecision(CandidateFPU.Restriction)) {
417 return ARM::FK_INVALID;
420 bool ARM::appendArchExtFeatures(StringRef CPU, ARM::ArchKind AK,
423 ARM::FPUKind &ArgFPUKind) {
446 const ARM::FPUKind DefaultFPU = getDefaultFPU(CPU, AK);
447 ARM::FPUKind FPUKind;
449 const bool IsDP = ArgFPUKind != ARM::FK_INVALID &&
450 ArgFPUKind != ARM::FK_NONE &&
456 if (ArgFPUKind != ARM::FK_INVALID && !IsDP)
459 if (FPUKind == ARM::FK_INVALID)
460 FPUKind = ARM::FK_NONE;
465 if (FPUKind == ARM::FK_INVALID)
469 FPUKind = ARM::FK_NONE;
479 ARM::ArchKind ARM::convertV9toV8(ARM::ArchKind AK) {
481 return ARM::ArchKind::INVALID;
482 if (AK < ARM::ArchKind::ARMV9A || AK > ARM::ArchKind::ARMV9_3A)
483 return ARM::ArchKind::INVALID;
484 unsigned AK_v8 = static_cast<unsigned>(ARM::ArchKind::ARMV8_5A);
486 static_cast<unsigned>(ARM::ArchKind::ARMV9A);
487 return static_cast<ARM::ArchKind>(AK_v8);
490 StringRef ARM::getDefaultCPU(StringRef Arch) {
505 uint64_t ARM::parseHWDiv(StringRef HWDiv) {
514 uint64_t ARM::parseArchExt(StringRef ArchExt) {
522 ARM::ArchKind ARM::parseCPUArch(StringRef CPU) {
530 void ARM::fillValidCPUArchList(SmallVectorImpl<StringRef> &Values) {
537 StringRef ARM::computeDefaultTargetABI(const Triple &TT, StringRef CPU) {
577 StringRef ARM::getARMCPUForArch(const llvm::Triple &Triple, StringRef MArch) {
580 MArch = llvm::ARM::getCanonicalArchName(MArch);
595 if (llvm::ARM::parseArchVersion(MArch) <= 7)
614 StringRef CPU = llvm::ARM::getDefaultCPU(MArch);
651 void ARM::PrintSupportedExtensions(StringMap<StringRef> DescMap) {
652 outs() << "All available -march extensions for ARM\n\n"