Lines Matching refs:Num
101 // LLVM register Num, which has kind Kind. In some ways it might be
112 unsigned Num;
174 createReg(RegisterKind Kind, unsigned Num, SMLoc StartLoc, SMLoc EndLoc) {
177 Op->Reg.Num = Num;
232 return Reg.Num;
408 unsigned Num;
785 if (Name.substr(1).getAsInteger(10, Reg.Num)) {
792 if (Prefix == 'r' && Reg.Num < 16)
794 else if (Prefix == 'f' && Reg.Num < 16)
796 else if (Prefix == 'v' && Reg.Num < 32)
798 else if (Prefix == 'a' && Reg.Num < 16)
800 else if (Prefix == 'c' && Reg.Num < 16)
887 if (Regs[Reg.Num] == 0)
891 SystemZOperand::createReg(Kind, Regs[Reg.Num], Reg.StartLoc, Reg.EndLoc));
924 if (Reg.Num > 15)
932 RegNo = SystemZMC::GR64Regs[Reg.Num];
936 RegNo = SystemZMC::FP64Regs[Reg.Num];
940 RegNo = SystemZMC::VR128Regs[Reg.Num];
944 RegNo = SystemZMC::AR32Regs[Reg.Num];
948 RegNo = SystemZMC::CR64Regs[Reg.Num];
980 Reg.Num = (unsigned)Value;
1126 Base = Reg1.Num == 0 ? 0 : Regs[Reg1.Num];
1140 Index = Reg1.Num == 0 ? 0 : Regs[Reg1.Num];
1142 Base = Reg1.Num == 0 ? 0 : Regs[Reg1.Num];
1148 Base = Reg2.Num == 0 ? 0 : Regs[Reg2.Num];
1156 Base = Reg2.Num == 0 ? 0 : Regs[Reg2.Num];
1169 LengthReg = SystemZMC::GR64Regs[Reg1.Num];
1174 Base = Reg2.Num == 0 ? 0 : Regs[Reg2.Num];
1181 Index = SystemZMC::VR128Regs[Reg1.Num];
1186 Base = Reg2.Num == 0 ? 0 : Regs[Reg2.Num];
1363 RegNo = SystemZMC::GR64Regs[Reg.Num];
1365 RegNo = SystemZMC::FP64Regs[Reg.Num];
1367 RegNo = SystemZMC::VR128Regs[Reg.Num];
1369 RegNo = SystemZMC::AR32Regs[Reg.Num];
1371 RegNo = SystemZMC::CR64Regs[Reg.Num];