Lines Matching defs:Cond

75                          const SmallVectorImpl<MachineOperand> &Cond,
77   assert(Cond.size() == 3 && "Unexpected number of operands");
79   auto CC = static_cast<RISCVCC::CondCode>(Cond[0].getImm());
80   if (CC == RISCVCC::COND_EQ && Cond[2].isReg() &&
81       Cond[2].getReg() == RISCV::X0 && TBB == &MBB)
83   if (CC == RISCVCC::COND_NE && Cond[2].isReg() &&
84       Cond[2].getReg() == RISCV::X0 && TBB != &MBB)
101   SmallVector<MachineOperand, 3> Cond;
102   if (TII->analyzeBranch(*PredMBB, TBB, FBB, Cond, /*AllowModify*/ false) ||
103       Cond.empty())
107   if (!guaranteesZeroRegInBlock(MBB, Cond, TBB))
110   Register TargetReg = Cond[1].getReg();