Lines Matching defs:auto
165 auto addRegClassForRVV = [this](MVT VT) {
214 auto addRegClassForFixedVectors = [this](MVT VT) {
968 const auto SetCommonVFPActions = [&](MVT VT) {
1045 const auto SetCommonVFPExtLoadTruncStoreActions =
1047 for (auto SmallVT : SmallerVTs) {
1569 auto &DL = I.getDataLayout();
1571 auto SetRVVLoadStoreInfo = [&](unsigned PtrOp, bool IsStore,
1918 if (auto *LD = dyn_cast<LoadSDNode>(Val)) {
1977 auto *C = dyn_cast<ConstantSDNode>(Y);
2088 auto *II = dyn_cast<IntrinsicInst>(I);
2158 for (auto OpIdx : enumerate(I->operands())) {
2412 if (auto *RHSC = dyn_cast<ConstantSDNode>(RHS)) {
2773 const auto [MinVLMAX, MaxVLMAX] =
2976 auto [Mask, VL] = getDefaultVLOps(DstVT, DstContainerVT, DL, DAG, Subtarget);
3162 auto [Mask, VL] = getDefaultVLOps(VT, ContainerVT, DL, DAG, Subtarget);
3292 auto [Mask, VL] = getDefaultVLOps(VT, ContainerVT, DL, DAG, Subtarget);
3386 for (auto [Idx, Elt] : enumerate(Op->op_values())) {
3394 auto ExactInteger =
3402 for (auto [Idx, Elt] : enumerate(Elts)) {
3452 for (auto [Idx, Elt] : enumerate(Elts)) {
3493 auto [Mask, VL] = getDefaultVLOps(VT, ContainerVT, DL, DAG, Subtarget);
3521 auto [Mask, VL] = getDefaultVLOps(VT, ContainerVT, DL, DAG, Subtarget);
3546 if (auto *CFP = dyn_cast<ConstantFPSDNode>(V))
3582 auto OpCode =
3593 for (const auto &OpIdx : enumerate(Op->ops())) {
3628 auto [Mask, VL] = getDefaultVLOps(VT, ContainerVT, DL, DAG, Subtarget);
3723 if (auto SimpleVID = isSimpleVIDSequence(Op, Op.getScalarValueSizeInBits())) {
3800 for (const auto &OpIdx : enumerate(Op->op_values())) {
3801 const auto &SeqV = OpIdx.value();
3832 const auto *BV = cast<BuildVectorSDNode>(Op);
3857 for (const auto &SeqV : Sequence) {
3966 auto pack = [&](SDValue A, SDValue B) {
4027 auto [Mask, VL] = getDefaultVLOps(VT, ContainerVT, DL, DAG, Subtarget);
4056 if (auto Gather = matchSplatAsGather(Splat, VT, DL, DAG, Subtarget))
4072 if (const auto VLen = Subtarget.getRealVLen();
4089 auto OneVRegOfOps = ArrayRef(BuildVectorOps).slice(i, ElemsPerVReg);
4223 auto OpCode =
4268 auto InterVec = DAG.getNode(RISCVISD::VMV_V_X_VL, DL, InterVT,
4577 auto [TrueMask, VL] = getDefaultVLOps(VT, ContainerVT, DL, DAG, Subtarget);
4623 auto findNonEXTRACT_SUBVECTORParent =
4636 auto [V1Src, V1IndexOffset] = findNonEXTRACT_SUBVECTORParent(V1);
4637 auto [V2Src, V2IndexOffset] = findNonEXTRACT_SUBVECTORParent(V2);
4672 auto [TrueMask, VL] = getDefaultVLOps(SrcVT, ContainerVT, DL, DAG, Subtarget);
4712 auto TrueMask = getDefaultVLOps(VT, ContainerVT, DL, DAG, Subtarget).first;
4757 auto isSlideMask = [](ArrayRef<int> Mask, unsigned Base, int Offset) {
4777 auto [TrueMask, VL] = getDefaultVLOps(VT, ContainerVT, DL, DAG, Subtarget);
4778 auto OpCode = IsVSlidedown ?
4783 auto Vec = DAG.getNode(OpCode, DL, ContainerVT,
4823 auto [Mask, VL] = getDefaultVLOps(VecVT, VecContainerVT, DL, DAG, Subtarget);
5008 const auto VLen = Subtarget.getRealVLen();
5061 auto &[SrcVecIdx, SrcSubMask] = OutMasks[DstVecIdx];
5108 auto [TrueMask, VL] = getDefaultVLOps(VT, ContainerVT, DL, DAG, Subtarget);
5130 auto *Ld = cast<LoadSDNode>(V);
5293 any_of(Mask, [&](const auto &Idx) { return Idx > 255; })) {
5563 auto *Load = cast<LoadSDNode>(Op);
5592 auto *Store = cast<StoreSDNode>(Op);
5796 auto [Mask, VL] = getDefaultScalableVLOps(VT0, DL, DAG, Subtarget);
5816 auto [Mask, VL] = getDefaultVLOps(VT0, ContainerVT0, DL, DAG, Subtarget);
6138 auto [LoVT, HiVT] = DAG.GetSplitDestVTs(Op.getValueType());
6164 auto [LoVT, HiVT] = DAG.GetSplitDestVTs(Op.getValueType());
6196 auto [Lo, Hi] = DAG.SplitVector(Op.getOperand(1), DL);
6197 auto [MaskLo, MaskHi] = DAG.SplitVector(Op.getOperand(2), DL);
6198 auto [EVLLo, EVLHi] =
6212 auto [LoVT, HiVT] = DAG.GetSplitDestVTs(Op->getValueType(0));
6610 auto [FExt, Chain] =
6691 auto [Mask, VL] = getDefaultVLOps(VT, ContainerVT, DL, DAG, Subtarget);
6897 for (const auto &OpIdx : enumerate(Op->ops())) {
6909 if (auto V = expandUnalignedRVVLoad(Op, DAG))
6915 if (auto V = expandUnalignedRVVStore(Op, DAG))
7179 auto NC = DAG.getNode(Op.getOpcode(), DL, NVT, Op->ops());
8096 auto VL = getDefaultVLOps(VecVT, ContainerVT, DL, DAG, Subtarget).second;
8169 auto [Mask, VL] = getDefaultVLOps(VT, ContainerVT, DL, DAG, Subtarget);
8309 auto [Mask, VL] = getDefaultVLOps(SrcVT, ContainerVT, DL, DAG, Subtarget);
8475 if (auto *IdxC = dyn_cast<ConstantSDNode>(Idx)) {
8478 if (auto ShrunkVT = getSmallestVTForIndex(ContainerVT, OrigIdx,
8488 if (auto VLEN = Subtarget.getRealVLen();
8514 const auto *CVal = cast<ConstantSDNode>(Val);
8521 auto [Mask, VL] = getDefaultVLOps(VecVT, ContainerVT, DL, DAG, Subtarget);
8631 auto [Mask, VL] = getDefaultVLOps(VecVT, ContainerVT, DL, DAG, Subtarget);
8696 const auto VLen = Subtarget.getRealVLen();
8697 if (auto *IdxC = dyn_cast<ConstantSDNode>(Idx);
8718 if (auto *IdxC = dyn_cast<ConstantSDNode>(Idx))
8721 if (auto SmallerVT =
8748 auto [Mask, VL] = getDefaultVLOps(1, ContainerVT, DL, DAG, Subtarget);
8852 const auto [MinVLMAX, MaxVLMAX] =
8999 auto [Mask, VL] = getDefaultVLOps(OpVT, ContainerVT, DL, DAG, Subtarget);
9432 auto *Load = cast<MemIntrinsicSDNode>(Op);
9506 auto *Load = cast<MemIntrinsicSDNode>(Op);
9591 auto *Store = cast<MemIntrinsicSDNode>(Op);
9629 auto *FixedIntrinsic = cast<MemIntrinsicSDNode>(Op);
9794 auto *RegisterAVL = dyn_cast<RegisterSDNode>(AVL);
9795 auto *ImmAVL = dyn_cast<ConstantSDNode>(AVL);
9813 auto InnerVT = VecVT.bitsLE(M1VT) ? VecVT : M1VT;
9817 auto InnerVL = NonZeroAVL ? VL : DAG.getConstant(1, DL, XLenVT);
9844 auto [Lo, Hi] = DAG.SplitVector(Vec, DL);
9864 auto [Mask, VL] = getDefaultVLOps(VecVT, ContainerVT, DL, DAG, Subtarget);
9888 auto Flags = Op->getFlags();
9936 auto [Mask, VL] = getDefaultVLOps(VecVT, ContainerVT, DL, DAG, Subtarget);
9979 auto ContainerVT = getContainerForFixedLengthVector(VecVT);
10065 const auto VLen = Subtarget.getRealVLen();
10134 auto Decompose =
10141 auto Decompose =
10208 auto [Mask, VL] = getDefaultVLOps(VecVT, ContainerVecVT, DL, DAG, Subtarget);
10301 const auto VLen = Subtarget.getRealVLen();
10317 if (auto ShrunkVT =
10357 auto Decompose =
10364 auto Decompose =
10402 auto [Mask, VL] = getDefaultScalableVLOps(InterSubVT, DL, DAG, Subtarget);
10465 auto [Op0Lo, Op0Hi] = DAG.SplitVectorOperand(Op.getNode(), 0);
10466 auto [Op1Lo, Op1Hi] = DAG.SplitVectorOperand(Op.getNode(), 1);
10489 auto [Mask, VL] = getDefaultScalableVLOps(ConcatVT, DL, DAG, Subtarget);
10543 auto [Op0Lo, Op0Hi] = DAG.SplitVectorOperand(Op.getNode(), 0);
10544 auto [Op1Lo, Op1Hi] = DAG.SplitVectorOperand(Op.getNode(), 1);
10623 auto [Mask, VL] = getDefaultScalableVLOps(VT, DL, DAG, Subtarget);
10676 auto [Lo, Hi] = DAG.SplitVectorOperand(Op.getNode(), 0);
10677 auto [LoVT, HiVT] = DAG.GetSplitDestVTs(VecVT);
10696 auto [Mask, VL] = getDefaultScalableVLOps(VecVT, DL, DAG, Subtarget);
10759 auto *Load = cast<LoadSDNode>(Op);
10772 const auto [MinVLMAX, MaxVLMAX] =
10808 auto *Store = cast<StoreSDNode>(Op);
10835 const auto [MinVLMAX, MaxVLMAX] =
10862 const auto *MemSD = cast<MemSDNode>(Op);
10869 if (const auto *VPLoad = dyn_cast<VPLoadSDNode>(Op)) {
10874 const auto *MLoad = cast<MaskedLoadSDNode>(Op);
10926 const auto *MemSD = cast<MemSDNode>(Op);
10934 if (const auto *VPStore = dyn_cast<VPStoreSDNode>(Op)) {
10939 const auto *MStore = cast<MaskedStoreSDNode>(Op);
11001 auto [Mask, VL] = getDefaultVLOps(VT.getVectorNumElements(), ContainerVT, DL,
11062 auto [Mask, VL] = getDefaultVLOps(InVT, ContainerInVT, DL, DAG, Subtarget);
11151 auto [Mask, VL] = getDefaultVLOps(VT, ContainerVT, DL, DAG, Subtarget);
11210 auto [Mask, VL] = getDefaultVLOps(VT, ContainerVT, DL, DAG, Subtarget);
11249 for (const auto &OpIdx : enumerate(Op->ops())) {
11255 auto MaskIdx = ISD::getVPMaskIdx(Op.getOpcode());
11701 auto [LoVT, HiVT] = DAG.GetSplitDestVTs(GatherVT);
11702 auto [Lo, Hi] = DAG.SplitVector(Op1, DL);
11803 auto *VPNode = cast<VPStridedLoadSDNode>(Op);
11843 auto *VPNode = cast<VPStridedStoreSDNode>(Op);
11886 const auto *MemSD = cast<MemSDNode>(Op.getNode());
11895 if (auto *VPGN = dyn_cast<VPGatherSDNode>(Op.getNode())) {
11904 auto *MGN = cast<MaskedGatherSDNode>(Op.getNode());
11983 const auto *MemSD = cast<MemSDNode>(Op.getNode());
11992 if (auto *VPSN = dyn_cast<VPScatterSDNode>(Op.getNode())) {
12001 auto *MSN = cast<MaskedScatterSDNode>(Op.getNode());
12352 auto MakeMULPair = [&](SDValue S, SDValue U) {
12691 auto [Mask, VL] = getDefaultVLOps(1, ContainerVT, DL, DAG, Subtarget);
12864 auto [Mask, VL] = getDefaultVLOps(1, VecVT, DL, DAG, Subtarget);
13033 auto Flags = ReduceVec->getFlags();
13045 auto BinOpToRVVReduce = [](unsigned Opc) {
13074 auto IsReduction = [&BinOpToRVVReduce](SDValue V, unsigned Opc) {
13168 auto *N0C = dyn_cast<ConstantSDNode>(N0->getOperand(1));
13169 auto *N1C = dyn_cast<ConstantSDNode>(N1->getOperand(1));
13234 auto isZeroOrAllOnes = [](SDValue N, bool AllOnes) {
13310 auto *N0C = dyn_cast<ConstantSDNode>(N0->getOperand(1));
13311 auto *N1C = dyn_cast<ConstantSDNode>(N->getOperand(1));
13456 auto *N0C = dyn_cast<ConstantSDNode>(N0);
13507 auto *ShAmtC = dyn_cast<ConstantSDNode>(N0.getOperand(1));
13825 auto *ConstN00 = dyn_cast<ConstantSDNode>(N0.getOperand(0));
14071 auto IsAddSubWith1 = [&](SDValue V) -> bool {
14185 auto *N1C = dyn_cast<ConstantSDNode>(N1);
14337 auto [Mask, VL] = getMaskAndVL(Root, DAG, Subtarget);
15006 auto AppendUsersIfNeeded = [&Worklist,
15161 auto Ext = cast<LoadSDNode>(LSNode1)->getExtensionType();
15216 auto ExtractBaseAndOffset = [](SDValue Ptr) -> std::pair<SDValue, uint64_t> {
15218 if (auto *C1 = dyn_cast<ConstantSDNode>(Ptr->getOperand(1)))
15223 auto [Base1, Offset1] = ExtractBaseAndOffset(LSNode1->getOperand(OpNum));
15246 auto [Base2, Offset2] = ExtractBaseAndOffset(LSNode2->getOperand(OpNum));
15336 auto [Mask, VL] =
15518 auto invertIfNegative = [&Mask, &VL](SDValue &V) {
15972 auto AndNode = DAG.getNode(ISD::AND, SDLoc(N), CountZeroes.getValueType(),
16135 auto *IndexC = dyn_cast<ConstantSDNode>(EltNo);
16175 auto *BaseLd = dyn_cast<LoadSDNode>(N->getOperand(0));
16187 auto *Ld = dyn_cast<LoadSDNode>(Op);
16200 auto GetPtrDiff = [&DAG](LoadSDNode *Ld1,
16221 auto BaseDiff = GetPtrDiff(Lds[0], Lds[1]);
16226 for (auto *It = Lds.begin() + 1; It != Lds.end() - 1; It++)
16248 auto [StrideVariant, MustNegateStride] = *BaseDiff;
16261 if (auto *ConstStride = dyn_cast<ConstantSDNode>(Stride);
16303 auto IsVWMulOpc = [](unsigned Opc) {
16325 auto [AddMask, AddVL] = [](SDNode *N, SelectionDAG &DAG,
16484 auto IsTruncNode = [&](SDValue V) {
16536 auto MatchMinMax = [&VL, &Mask](SDValue V, unsigned Opc, unsigned OpcVL,
16559 if (auto *Op1 = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
16571 auto DetectUSatPattern = [&](SDValue V) {
16602 auto DetectSSatPattern = [&](SDValue V) {
16666 auto SimplifyDemandedLowBitsHelper = [&](unsigned OpNo, unsigned LowBits) {
17063 const auto *MGN = cast<MaskedGatherSDNode>(N);
17144 auto EltCnt = VT.getVectorElementCount();
17164 const auto *MSN = cast<MaskedScatterSDNode>(N);
17200 const auto *VPGN = cast<VPGatherSDNode>(N);
17225 const auto *VPSN = cast<VPScatterSDNode>(N);
17329 auto *Store = cast<StoreSDNode>(N);
17379 if (auto *L = dyn_cast<LoadSDNode>(Val);
17428 if (auto Gather = matchSplatAsGather(N->getOperand(0), VT.getSimpleVT(), N,
17554 auto *Load = cast<MemIntrinsicSDNode>(N);
17563 if (auto *StrideC = dyn_cast<ConstantSDNode>(Stride);
17572 auto *Store = cast<MemIntrinsicSDNode>(N);
17581 if (auto *StrideC = dyn_cast<ConstantSDNode>(Stride);
17668 auto *C1 = dyn_cast<ConstantSDNode>(N0->getOperand(1));
17669 auto *C2 = dyn_cast<ConstantSDNode>(N->getOperand(1));
17733 auto IsLegalMask = [ShrunkMask, ExpandedMask](const APInt &Mask) -> bool {
17736 auto UseMask = [Mask, Op, &TLO](const APInt &NewMask) -> bool {
17932 auto [LMul, Fractional] = RISCVVType::decodeVLMUL(VLMUL);
18063 auto GetSupportedConstantPool = [](SDValue Ptr) -> ConstantPoolSDNode * {
18064 auto *CNode = dyn_cast<ConstantPoolSDNode>(Ptr);
18074 auto *CNode = GetSupportedConstantPool(Ptr);
18086 auto *CNodeLo = GetSupportedConstantPool(Ptr.getOperand(1));
18087 auto *CNodeHi = GetSupportedConstantPool(Ptr.getOperand(0).getOperand(0));
18267 auto MIB = BuildMI(*BB, MI, DL, TII.get(RelOpcode), DstReg)
18278 auto MIB2 = BuildMI(*BB, MI, DL, TII.get(EqOpcode), RISCV::X0)
18355 auto FirstCC = static_cast<RISCVCC::CondCode>(First.getOperand(3).getImm());
18369 auto SecondCC = static_cast<RISCVCC::CondCode>(Second.getOperand(3).getImm());
18425 auto Next = next_nodbg(MI.getIterator(), BB->instr_end());
18437 auto CC = static_cast<RISCVCC::CondCode>(MI.getOperand(3).getImm());
18444 for (auto E = BB->end(), SequenceMBBI = MachineBasicBlock::iterator(MI);
18520 auto SelectMBBI = MI.getIterator();
18521 auto SelectEnd = std::next(LastSelectPseudo->getIterator());
18522 auto InsertionPoint = TailMBB->begin();
18524 auto Next = std::next(SelectMBBI);
18709 auto MIB =
19204 for (auto &It : PendingLocs) {
19238 for (const auto &ArgIdx : enumerate(Args)) {
19580 auto StackAlign =
19831 auto CalleeCC = CLI.CallConv;
19832 auto &Outs = CLI.Outs;
19833 auto &Caller = MF.getFunction();
19834 auto CallerCC = Caller.getCallingConv();
19856 for (auto &VA : ArgLocs)
19862 auto IsCallerStructRet = Caller.hasStructRetAttr();
19863 auto IsCalleeStructRet = Outs.empty() ? false : Outs[0].Flags.isSRet();
19879 for (auto &Arg : Outs)
20043 for (const auto &Part : Parts) {
20089 for (auto &Reg : RegsToPass) {
20121 for (auto &Reg : RegsToPass)
20168 auto &VA = RVLocs[i];
20322 if (llvm::any_of(Regs, [&STI](auto Reg) {
20694 for (const auto *RC : {&RISCV::VRRegClass, &RISCV::VRM2RegClass,
20844 for (const auto *RC :
20891 if (auto *C = dyn_cast<ConstantSDNode>(Op)) {
20906 if (auto *C = dyn_cast<ConstantSDNode>(Op)) {
21359 if (auto *ConstNode = dyn_cast<ConstantSDNode>(C.getNode())) {
21634 if (auto *FVTy = dyn_cast<FixedVectorType>(VTy)) {
21651 auto [LMUL, Fractional] = RISCVVType::decodeVLMUL(getLMUL(ContainerVT));
21700 auto *VTy = cast<FixedVectorType>(Shuffles[0]->getType());
21706 auto *XLenTy = Type::getIntNTy(LI->getContext(), Subtarget.getXLen());
21751 auto *ShuffleVTy = cast<FixedVectorType>(SVI->getType());
21753 auto *VTy = FixedVectorType::get(ShuffleVTy->getElementType(),
21760 auto *XLenTy = Type::getIntNTy(SI->getContext(), Subtarget.getXLen());
21766 auto Mask = SVI->getShuffleMask();
21810 if (auto *FVTy = dyn_cast<FixedVectorType>(VTy)) {
21859 if (auto *FVTy = dyn_cast<FixedVectorType>(VTy)) {
22047 auto isHomogeneousScalableVectorType = [](ArrayRef<Arg> ArgList) {
22049 auto It = ArgList.begin();
22078 for (const auto &OutArg : ArgList) {
22185 auto allocate = [&](const RVVArgInfo &ArgInfo) {