Lines Matching defs:RegisterRef
178 // FIXME: Consolidate duplicate definitions of RegisterRef
179 struct RegisterRef {
180 RegisterRef(const MachineOperand &Op) : Reg(Op.getReg()),
182 RegisterRef(unsigned R = 0, unsigned S = 0) : Reg(R), Sub(S) {}
184 bool operator== (RegisterRef RR) const {
187 bool operator!= (RegisterRef RR) const { return !operator==(RR); }
188 bool operator< (RegisterRef RR) const {
204 void addRefToMap(RegisterRef RR, ReferenceMap &Map, unsigned Exec);
205 bool isRefInMap(RegisterRef, ReferenceMap &Map, unsigned Exec);
224 MachineInstr *getReachingDefForPred(RegisterRef RD,
232 void renameInRange(RegisterRef RO, RegisterRef RN, unsigned PredR,
238 bool isIntReg(RegisterRef RR, unsigned &BW);
240 bool coalesceRegisters(RegisterRef R1, RegisterRef R2);
297 void HexagonExpandCondsets::addRefToMap(RegisterRef RR, ReferenceMap &Map,
307 bool HexagonExpandCondsets::isRefInMap(RegisterRef RR, ReferenceMap &Map,
472 std::set<RegisterRef> DefRegs;
499 std::map<RegisterRef,unsigned> ImpUses;
606 RegisterRef RS = SO;
665 if (RegisterRef(SrcOp) == RegisterRef(DstR, DstSR))
713 RegisterRef RT(ST);
714 if (RT == RegisterRef(SF)) {
768 MachineInstr *HexagonExpandCondsets::getReachingDefForPred(RegisterRef RD,
792 RegisterRef RR = Op;
826 RegisterRef RR = Op;
932 void HexagonExpandCondsets::renameInRange(RegisterRef RO, RegisterRef RN,
946 if (!Op.isReg() || RO != RegisterRef(Op))
981 RegisterRef RT(MS);
1026 RegisterRef RR = Op;
1057 RegisterRef RD = MD;
1104 if (RegisterRef(MI.getOperand(0)) == RegisterRef(MI.getOperand(2))) {
1118 bool HexagonExpandCondsets::isIntReg(RegisterRef RR, unsigned &BW) {
1145 bool HexagonExpandCondsets::coalesceRegisters(RegisterRef R1, RegisterRef R2) {
1225 RegisterRef RD = CI->getOperand(0);
1226 RegisterRef RP = CI->getOperand(1);
1248 RegisterRef RS = S1;
1251 Done = coalesceRegisters(RD, RegisterRef(S1));
1259 RegisterRef RS = S2;
1262 Done = coalesceRegisters(RD, RegisterRef(S2));