Lines Matching full:arm
54 return MCInstBuilder(ARM::tHINT).addImm(0).addImm(ARMCC::AL).addReg(0);
93 if (MBBI->getOpcode() == ARM::t2IT) {
141 get(ARM::t2CSEL), DestReg)
156 if (!ARM::GPRRegClass.contains(DestReg, SrcReg))
159 BuildMI(MBB, I, DL, get(ARM::tMOVr), DestReg)
179 if (ARM::GPRRegClass.hasSubClassEq(RC)) {
180 BuildMI(MBB, I, DL, get(ARM::t2STRi12))
189 if (ARM::GPRPairRegClass.hasSubClassEq(RC)) {
195 MRI->constrainRegClass(SrcReg, &ARM::GPRPairnospRegClass);
198 MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(ARM::t2STRDi8));
199 AddDReg(MIB, SrcReg, ARM::gsub_0, getKillRegState(isKill), TRI);
200 AddDReg(MIB, SrcReg, ARM::gsub_1, 0, TRI);
223 if (ARM::GPRRegClass.hasSubClassEq(RC)) {
224 BuildMI(MBB, I, DL, get(ARM::t2LDRi12), DestReg)
232 if (ARM::GPRPairRegClass.hasSubClassEq(RC)) {
238 MRI->constrainRegClass(DestReg, &ARM::GPRPairnospRegClass);
241 MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(ARM::t2LDRDi8));
242 AddDReg(MIB, DestReg, ARM::gsub_0, RegState::DefineNoRead, TRI);
243 AddDReg(MIB, DestReg, ARM::gsub_1, RegState::DefineNoRead, TRI);
261 expandLoadStackGuardBase(MI, ARM::t2MRC, ARM::t2LDRi12);
267 expandLoadStackGuardBase(MI, ARM::t2LDRLIT_ga_pcrel, ARM::t2LDRi12);
269 expandLoadStackGuardBase(MI, ARM::t2MOV_ga_pcrel, ARM::t2LDRi12);
271 expandLoadStackGuardBase(MI, ARM::t2MOVi32imm, ARM::t2LDRi12);
279 case ARM::MVE_VMAXNMAf16:
280 case ARM::MVE_VMAXNMAf32:
281 case ARM::MVE_VMINNMAf16:
282 case ARM::MVE_VMINNMAf32:
298 case ARM::t2BTI:
299 case ARM::t2PAC:
300 case ARM::t2PACBTI:
301 case ARM::t2SG:
317 BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr), DestReg)
328 if (DestReg != ARM::SP && DestReg != BaseReg &&
334 BuildMI(MBB, MBBI, dl, TII.get(ARM::t2MOVi16), DestReg)
340 BuildMI(MBB, MBBI, dl, TII.get(ARM::t2MOVTi16), DestReg)
349 BuildMI(MBB, MBBI, dl, TII.get(ARM::t2SUBrr), DestReg)
361 BuildMI(MBB, MBBI, dl, TII.get(ARM::t2ADDrr), DestReg)
375 if (DestReg == ARM::SP && BaseReg != ARM::SP) {
377 BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr), DestReg)
381 BaseReg = ARM::SP;
385 assert((DestReg != ARM::SP || BaseReg == ARM::SP) &&
389 if ((DestReg == ARM::SP) && (ThisVal < ((1 << 7) - 1) * 4)) {
391 Opc = isSub ? ARM::tSUBspi : ARM::tADDspi;
401 bool ToSP = DestReg == ARM::SP;
402 unsigned t2SUB = ToSP ? ARM::t2SUBspImm : ARM::t2SUBri;
403 unsigned t2ADD = ToSP ? ARM::t2ADDspImm : ARM::t2ADDri;
404 unsigned t2SUBi12 = ToSP ? ARM::t2SUBspImm12 : ARM::t2SUBri12;
405 unsigned t2ADDi12 = ToSP ? ARM::t2ADDspImm12 : ARM::t2ADDri12;
443 case ARM::t2LDRi12: return ARM::t2LDRi8;
444 case ARM::t2LDRHi12: return ARM::t2LDRHi8;
445 case ARM::t2LDRBi12: return ARM::t2LDRBi8;
446 case ARM::t2LDRSHi12: return ARM::t2LDRSHi8;
447 case ARM::t2LDRSBi12: return ARM::t2LDRSBi8;
448 case ARM::t2STRi12: return ARM::t2STRi8;
449 case ARM::t2STRBi12: return ARM::t2STRBi8;
450 case ARM::t2STRHi12: return ARM::t2STRHi8;
451 case ARM::t2PLDi12: return ARM::t2PLDi8;
452 case ARM::t2PLDWi12: return ARM::t2PLDWi8;
453 case ARM::t2PLIi12: return ARM::t2PLIi8;
455 case ARM::t2LDRi8:
456 case ARM::t2LDRHi8:
457 case ARM::t2LDRBi8:
458 case ARM::t2LDRSHi8:
459 case ARM::t2LDRSBi8:
460 case ARM::t2STRi8:
461 case ARM::t2STRBi8:
462 case ARM::t2STRHi8:
463 case ARM::t2PLDi8:
464 case ARM::t2PLDWi8:
465 case ARM::t2PLIi8:
477 case ARM::t2LDRi8: return ARM::t2LDRi12;
478 case ARM::t2LDRHi8: return ARM::t2LDRHi12;
479 case ARM::t2LDRBi8: return ARM::t2LDRBi12;
480 case ARM::t2LDRSHi8: return ARM::t2LDRSHi12;
481 case ARM::t2LDRSBi8: return ARM::t2LDRSBi12;
482 case ARM::t2STRi8: return ARM::t2STRi12;
483 case ARM::t2STRBi8: return ARM::t2STRBi12;
484 case ARM::t2STRHi8: return ARM::t2STRHi12;
485 case ARM::t2PLDi8: return ARM::t2PLDi12;
486 case ARM::t2PLDWi8: return ARM::t2PLDWi12;
487 case ARM::t2PLIi8: return ARM::t2PLIi12;
489 case ARM::t2LDRi12:
490 case ARM::t2LDRHi12:
491 case ARM::t2LDRBi12:
492 case ARM::t2LDRSHi12:
493 case ARM::t2LDRSBi12:
494 case ARM::t2STRi12:
495 case ARM::t2STRBi12:
496 case ARM::t2STRHi12:
497 case ARM::t2PLDi12:
498 case ARM::t2PLDWi12:
499 case ARM::t2PLIi12:
511 case ARM::t2LDRs: return ARM::t2LDRi12;
512 case ARM::t2LDRHs: return ARM::t2LDRHi12;
513 case ARM::t2LDRBs: return ARM::t2LDRBi12;
514 case ARM::t2LDRSHs: return ARM::t2LDRSHi12;
515 case ARM::t2LDRSBs: return ARM::t2LDRSBi12;
516 case ARM::t2STRs: return ARM::t2STRi12;
517 case ARM::t2STRBs: return ARM::t2STRBi12;
518 case ARM::t2STRHs: return ARM::t2STRHi12;
519 case ARM::t2PLDs: return ARM::t2PLDi12;
520 case ARM::t2PLDWs: return ARM::t2PLDWi12;
521 case ARM::t2PLIs: return ARM::t2PLIi12;
523 case ARM::t2LDRi12:
524 case ARM::t2LDRHi12:
525 case ARM::t2LDRBi12:
526 case ARM::t2LDRSHi12:
527 case ARM::t2LDRSBi12:
528 case ARM::t2STRi12:
529 case ARM::t2STRBi12:
530 case ARM::t2STRHi12:
531 case ARM::t2PLDi12:
532 case ARM::t2PLDWi12:
533 case ARM::t2PLIi12:
534 case ARM::t2LDRi8:
535 case ARM::t2LDRHi8:
536 case ARM::t2LDRBi8:
537 case ARM::t2LDRSHi8:
538 case ARM::t2LDRSBi8:
539 case ARM::t2STRi8:
540 case ARM::t2STRBi8:
541 case ARM::t2STRHi8:
542 case ARM::t2PLDi8:
543 case ARM::t2PLDWi8:
544 case ARM::t2PLIi8:
566 if (Opcode == ARM::INLINEASM || Opcode == ARM::INLINEASM_BR)
569 const bool IsSP = Opcode == ARM::t2ADDspImm12 || Opcode == ARM::t2ADDspImm;
570 if (IsSP || Opcode == ARM::t2ADDri || Opcode == ARM::t2ADDri12) {
575 !MI.definesRegister(ARM::CPSR, /*TRI=*/nullptr)) {
577 MI.setDesc(TII.get(ARM::tMOVr));
587 bool HasCCOut = (Opcode != ARM::t2ADDspImm12 && Opcode != ARM::t2ADDri12);
592 MI.setDesc(IsSP ? TII.get(ARM::t2SUBspImm) : TII.get(ARM::t2SUBri));
594 MI.setDesc(IsSP ? TII.get(ARM::t2ADDspImm) : TII.get(ARM::t2ADDri));
610 unsigned NewOpc = isSub ? IsSP ? ARM::t2SUBspImm12 : ARM::t2SUBri12
611 : IsSP ? ARM::t2ADDspImm12 : ARM::t2ADDri12;
789 if (Opc == ARM::tBcc || Opc == ARM::t2Bcc)
798 if (ARM::isVpred(MCID.operands()[i].OperandType))
837 ARM::PredBlockMask BlockMask = ARM::PredBlockMask::T;