Lines Matching full:arm
1 //===- ARMDisassembler.cpp - Disassembler for ARM/Thumb ISA ---------------===//
35 #define DEBUG_TYPE "arm-disassembler"
130 /// ARM disassembler for all ARM platforms.
138 InstructionEndianness = STI.hasFeature(ARM::ModeBigEndianInstructions)
721 case ARM::HVC: {
731 case ARM::t2ADDri:
732 case ARM::t2ADDri12:
733 case ARM::t2ADDrr:
734 case ARM::t2ADDrs:
735 case ARM::t2SUBri:
736 case ARM::t2SUBri12:
737 case ARM::t2SUBrr:
738 case ARM::t2SUBrs:
739 if (MI.getOperand(0).getReg() == ARM::SP &&
740 MI.getOperand(1).getReg() != ARM::SP)
749 // In Arm state, instructions are always 4 bytes wide, so there's no
752 if (!STI.hasFeature(ARM::ModeThumb))
779 if (STI.hasFeature(ARM::ModeThumb))
790 assert(!STI.hasFeature(ARM::ModeThumb) &&
791 "Asked to disassemble an ARM instruction but Subtarget is in Thumb "
894 MCID.operands()[i].RegClass == ARM::CCRRegClassID) {
897 MI.insert(I, MCOperand::createReg(InITBlock ? 0 : ARM::CPSR));
902 MI.insert(I, MCOperand::createReg(InITBlock ? 0 : ARM::CPSR));
908 if (ARM::isVpred(MCID.operands()[i].OperandType))
927 case ARM::tBcc:
928 case ARM::t2Bcc:
929 case ARM::tCBZ:
930 case ARM::tCBNZ:
931 case ARM::tCPS:
932 case ARM::t2CPS3p:
933 case ARM::t2CPS2p:
934 case ARM::t2CPS1p:
935 case ARM::t2CSEL:
936 case ARM::t2CSINC:
937 case ARM::t2CSINV:
938 case ARM::t2CSNEG:
939 case ARM::tMOVSr:
940 case ARM::tSETEND:
948 case ARM::t2HINT:
949 if (MI.getOperand(0).getImm() == 0x10 && (FeatureBits[ARM::FeatureRAS]) != 0)
952 case ARM::tB:
953 case ARM::t2B:
954 case ARM::t2TBB:
955 case ARM::t2TBH:
997 MI.insert(CCI, MCOperand::createReg(ARM::CPSR));
1005 if (ARM::isVpred(MCID.operands()[VCCPos].OperandType) || VCCI == MI.end())
1015 VCCI = MI.insert(VCCI, MCOperand::createReg(ARM::P0));
1019 if (MCID.operands()[VCCPos].OperandType == ARM::OPERAND_VPRED_R) {
1034 // encodings between ARM and Thumb modes, and they are predicable in ARM
1064 I->setReg(ARM::CPSR);
1076 assert(STI.hasFeature(ARM::ModeThumb) &&
1077 "Asked to disassemble in Thumb mode but Subtarget is in ARM mode!");
1112 if (MI.getOpcode() == ARM::t2IT && ITBlock.instrInITBlock())
1120 if (MI.getOpcode() == ARM::t2IT) {
1256 const uint8_t *DecoderTable = ARM::isCDECoproc(Coproc, STI)
1283 ARM::R0, ARM::R1, ARM::R2, ARM::R3,
1284 ARM::R4, ARM::R5, ARM::R6, ARM::R7,
1285 ARM::R8, ARM::R9, ARM::R10, ARM::R11,
1286 ARM::R12, ARM::SP, ARM::LR, ARM::PC
1290 ARM::R0, ARM::R1, ARM::R2, ARM::R3,
1291 ARM::R4, ARM::R5, ARM::R6, ARM::R7,
1292 ARM::R8, ARM::R9, ARM::R10, ARM::R11,
1293 ARM::R12, 0, ARM::LR, ARM::APSR
1354 Inst.addOperand(MCOperand::createReg(ARM::APSR_NZCV));
1369 Inst.addOperand(MCOperand::createReg(ARM::ZR));
1399 ARM::R0_R1, ARM::R2_R3, ARM::R4_R5, ARM::R6_R7,
1400 ARM::R8_R9, ARM::R10_R11, ARM::R12_SP
1408 // According to the Arm ARM RegNo = 14 is undefined, but we return fail
1452 Register = ARM::R0;
1455 Register = ARM::R1;
1458 Register = ARM::R2;
1461 Register = ARM::R3;
1464 Register = ARM::R9;
1467 Register = ARM::R12;
1485 if ((RegNo == 13 && !featureBits[ARM::HasV8Ops]) || RegNo == 15)
1493 ARM::S0, ARM::S1, ARM::S2, ARM::S3,
1494 ARM::S4, ARM::S5, ARM::S6, ARM::S7,
1495 ARM::S8, ARM::S9, ARM::S10, ARM::S11,
1496 ARM::S12, ARM::S13, ARM::S14, ARM::S15,
1497 ARM::S16, ARM::S17, ARM::S18, ARM::S19,
1498 ARM::S20, ARM::S21, ARM::S22, ARM::S23,
1499 ARM::S24, ARM::S25, ARM::S26, ARM::S27,
1500 ARM::S28, ARM::S29, ARM::S30, ARM::S31
1521 ARM::D0, ARM::D1, ARM::D2, ARM::D3,
1522 ARM::D4, ARM::D5, ARM::D6, ARM::D7,
1523 ARM::D8, ARM::D9, ARM::D10, ARM::D11,
1524 ARM::D12, ARM::D13, ARM::D14, ARM::D15,
1525 ARM::D16, ARM::D17, ARM::D18, ARM::D19,
1526 ARM::D20, ARM::D21, ARM::D22, ARM::D23,
1527 ARM::D24, ARM::D25, ARM::D26, ARM::D27,
1528 ARM::D28, ARM::D29, ARM::D30, ARM::D31
1537 bool hasD32 = featureBits[ARM::FeatureD32];
1572 ARM::Q0, ARM::Q1, ARM::Q2, ARM::Q3,
1573 ARM::Q4, ARM::Q5, ARM::Q6, ARM::Q7,
1574 ARM::Q8, ARM::Q9, ARM::Q10, ARM::Q11,
1575 ARM::Q12, ARM::Q13, ARM::Q14, ARM::Q15
1591 ARM::Q0, ARM::D1_D2, ARM::Q1, ARM::D3_D4, ARM::Q2, ARM::D5_D6,
1592 ARM::Q3, ARM::D7_D8, ARM::Q4, ARM::D9_D10, ARM::Q5, ARM::D11_D12,
1593 ARM::Q6, ARM::D13_D14, ARM::Q7, ARM::D15_D16, ARM::Q8, ARM::D17_D18,
1594 ARM::Q9, ARM::D19_D20, ARM::Q10, ARM::D21_D22, ARM::Q11, ARM::D23_D24,
1595 ARM::Q12, ARM::D25_D26, ARM::Q13, ARM::D27_D28, ARM::Q14, ARM::D29_D30,
1596 ARM::Q15
1611 ARM::D0_D2, ARM::D1_D3, ARM::D2_D4, ARM::D3_D5,
1612 ARM::D4_D6, ARM::D5_D7, ARM::D6_D8, ARM::D7_D9,
1613 ARM::D8_D10, ARM::D9_D11, ARM::D10_D12, ARM::D11_D13,
1614 ARM::D12_D14, ARM::D13_D15, ARM::D14_D16, ARM::D15_D17,
1615 ARM::D16_D18, ARM::D17_D19, ARM::D18_D20, ARM::D19_D21,
1616 ARM::D20_D22, ARM::D21_D23, ARM::D22_D24, ARM::D23_D25,
1617 ARM::D24_D26, ARM::D25_D27, ARM::D26_D28, ARM::D27_D29,
1618 ARM::D28_D30, ARM::D29_D31
1638 if (Inst.getOpcode() == ARM::tBcc && Val == 0xE)
1648 Inst.addOperand(MCOperand::createReg(ARM::CPSR));
1656 Inst.addOperand(MCOperand::createReg(ARM::CPSR));
1747 case ARM::LDMIA_UPD:
1748 case ARM::LDMDB_UPD:
1749 case ARM::LDMIB_UPD:
1750 case ARM::LDMDA_UPD:
1751 case ARM::t2LDMIA_UPD:
1752 case ARM::t2LDMDB_UPD:
1753 case ARM::t2STMIA_UPD:
1754 case ARM::t2STMDB_UPD:
1758 case ARM::t2CLRM:
1878 case ARM::LDC_OFFSET:
1879 case ARM::LDC_PRE:
1880 case ARM::LDC_POST:
1881 case ARM::LDC_OPTION:
1882 case ARM::LDCL_OFFSET:
1883 case ARM::LDCL_PRE:
1884 case ARM::LDCL_POST:
1885 case ARM::LDCL_OPTION:
1886 case ARM::STC_OFFSET:
1887 case ARM::STC_PRE:
1888 case ARM::STC_POST:
1889 case ARM::STC_OPTION:
1890 case ARM::STCL_OFFSET:
1891 case ARM::STCL_PRE:
1892 case ARM::STCL_POST:
1893 case ARM::STCL_OPTION:
1894 case ARM::t2LDC_OFFSET:
1895 case ARM::t2LDC_PRE:
1896 case ARM::t2LDC_POST:
1897 case ARM::t2LDC_OPTION:
1898 case ARM::t2LDCL_OFFSET:
1899 case ARM::t2LDCL_PRE:
1900 case ARM::t2LDCL_POST:
1901 case ARM::t2LDCL_OPTION:
1902 case ARM::t2STC_OFFSET:
1903 case ARM::t2STC_PRE:
1904 case ARM::t2STC_POST:
1905 case ARM::t2STC_OPTION:
1906 case ARM::t2STCL_OFFSET:
1907 case ARM::t2STCL_PRE:
1908 case ARM::t2STCL_POST:
1909 case ARM::t2STCL_OPTION:
1910 case ARM::t2LDC2_OFFSET:
1911 case ARM::t2LDC2L_OFFSET:
1912 case ARM::t2LDC2_PRE:
1913 case ARM::t2LDC2L_PRE:
1914 case ARM::t2STC2_OFFSET:
1915 case ARM::t2STC2L_OFFSET:
1916 case ARM::t2STC2_PRE:
1917 case ARM::t2STC2L_PRE:
1918 case ARM::LDC2_OFFSET:
1919 case ARM::LDC2L_OFFSET:
1920 case ARM::LDC2_PRE:
1921 case ARM::LDC2L_PRE:
1922 case ARM::STC2_OFFSET:
1923 case ARM::STC2L_OFFSET:
1924 case ARM::STC2_PRE:
1925 case ARM::STC2L_PRE:
1926 case ARM::t2LDC2_OPTION:
1927 case ARM::t2STC2_OPTION:
1928 case ARM::t2LDC2_POST:
1929 case ARM::t2LDC2L_POST:
1930 case ARM::t2STC2_POST:
1931 case ARM::t2STC2L_POST:
1932 case ARM::LDC2_POST:
1933 case ARM::LDC2L_POST:
1934 case ARM::STC2_POST:
1935 case ARM::STC2L_POST:
1937 (featureBits[ARM::HasV8_1MMainlineOps] &&
1946 if (featureBits[ARM::HasV8Ops] && (coproc != 14))
1955 case ARM::t2LDC2_OFFSET:
1956 case ARM::t2LDC2L_OFFSET:
1957 case ARM::t2LDC2_PRE:
1958 case ARM::t2LDC2L_PRE:
1959 case ARM::t2STC2_OFFSET:
1960 case ARM::t2STC2L_OFFSET:
1961 case ARM::t2STC2_PRE:
1962 case ARM::t2STC2L_PRE:
1963 case ARM::LDC2_OFFSET:
1964 case ARM::LDC2L_OFFSET:
1965 case ARM::LDC2_PRE:
1966 case ARM::LDC2L_PRE:
1967 case ARM::STC2_OFFSET:
1968 case ARM::STC2L_OFFSET:
1969 case ARM::STC2_PRE:
1970 case ARM::STC2L_PRE:
1971 case ARM::t2LDC_OFFSET:
1972 case ARM::t2LDCL_OFFSET:
1973 case ARM::t2LDC_PRE:
1974 case ARM::t2LDCL_PRE:
1975 case ARM::t2STC_OFFSET:
1976 case ARM::t2STCL_OFFSET:
1977 case ARM::t2STC_PRE:
1978 case ARM::t2STCL_PRE:
1979 case ARM::LDC_OFFSET:
1980 case ARM::LDCL_OFFSET:
1981 case ARM::LDC_PRE:
1982 case ARM::LDCL_PRE:
1983 case ARM::STC_OFFSET:
1984 case ARM::STCL_OFFSET:
1985 case ARM::STC_PRE:
1986 case ARM::STCL_PRE:
1990 case ARM::t2LDC2_POST:
1991 case ARM::t2LDC2L_POST:
1992 case ARM::t2STC2_POST:
1993 case ARM::t2STC2L_POST:
1994 case ARM::LDC2_POST:
1995 case ARM::LDC2L_POST:
1996 case ARM::STC2_POST:
1997 case ARM::STC2L_POST:
1998 case ARM::t2LDC_POST:
1999 case ARM::t2LDCL_POST:
2000 case ARM::t2STC_POST:
2001 case ARM::t2STCL_POST:
2002 case ARM::LDC_POST:
2003 case ARM::LDCL_POST:
2004 case ARM::STC_POST:
2005 case ARM::STCL_POST:
2016 case ARM::LDC_OFFSET:
2017 case ARM::LDC_PRE:
2018 case ARM::LDC_POST:
2019 case ARM::LDC_OPTION:
2020 case ARM::LDCL_OFFSET:
2021 case ARM::LDCL_PRE:
2022 case ARM::LDCL_POST:
2023 case ARM::LDCL_OPTION:
2024 case ARM::STC_OFFSET:
2025 case ARM::STC_PRE:
2026 case ARM::STC_POST:
2027 case ARM::STC_OPTION:
2028 case ARM::STCL_OFFSET:
2029 case ARM::STCL_PRE:
2030 case ARM::STCL_POST:
2031 case ARM::STCL_OPTION:
2058 case ARM::STR_POST_IMM:
2059 case ARM::STR_POST_REG:
2060 case ARM::STRB_POST_IMM:
2061 case ARM::STRB_POST_REG:
2062 case ARM::STRT_POST_REG:
2063 case ARM::STRT_POST_IMM:
2064 case ARM::STRBT_POST_REG:
2065 case ARM::STRBT_POST_IMM:
2078 case ARM::LDR_POST_IMM:
2079 case ARM::LDR_POST_REG:
2080 case ARM::LDRB_POST_IMM:
2081 case ARM::LDRB_POST_REG:
2082 case ARM::LDRBT_POST_REG:
2083 case ARM::LDRBT_POST_IMM:
2084 case ARM::LDRT_POST_REG:
2085 case ARM::LDRT_POST_IMM:
2195 if (Inst.getOpcode() != ARM::TSB && Inst.getOpcode() != ARM::t2TSB)
2225 case ARM::STRD:
2226 case ARM::STRD_PRE:
2227 case ARM::STRD_POST:
2228 case ARM::LDRD:
2229 case ARM::LDRD_PRE:
2230 case ARM::LDRD_POST:
2237 case ARM::STRD:
2238 case ARM::STRD_PRE:
2239 case ARM::STRD_POST:
2252 case ARM::STRH:
2253 case ARM::STRH_PRE:
2254 case ARM::STRH_POST:
2262 case ARM::LDRD:
2263 case ARM::LDRD_PRE:
2264 case ARM::LDRD_POST:
2279 case ARM::LDRH:
2280 case ARM::LDRH_PRE:
2281 case ARM::LDRH_POST:
2294 case ARM::LDRSH:
2295 case ARM::LDRSH_PRE:
2296 case ARM::LDRSH_POST:
2297 case ARM::LDRSB:
2298 case ARM::LDRSB_PRE:
2299 case ARM::LDRSB_POST:
2324 case ARM::STRD:
2325 case ARM::STRD_PRE:
2326 case ARM::STRD_POST:
2327 case ARM::STRH:
2328 case ARM::STRH_PRE:
2329 case ARM::STRH_POST:
2341 case ARM::STRD:
2342 case ARM::STRD_PRE:
2343 case ARM::STRD_POST:
2344 case ARM::LDRD:
2345 case ARM::LDRD_PRE:
2346 case ARM::LDRD_POST:
2357 case ARM::LDRD:
2358 case ARM::LDRD_PRE:
2359 case ARM::LDRD_POST:
2360 case ARM::LDRH:
2361 case ARM::LDRH_PRE:
2362 case ARM::LDRH_POST:
2363 case ARM::LDRSH:
2364 case ARM::LDRSH_PRE:
2365 case ARM::LDRSH_POST:
2366 case ARM::LDRSB:
2367 case ARM::LDRSB_PRE:
2368 case ARM::LDRSB_POST:
2369 case ARM::LDRHTr:
2370 case ARM::LDRSBTr:
2464 case ARM::LDMDA:
2465 Inst.setOpcode(ARM::RFEDA);
2467 case ARM::LDMDA_UPD:
2468 Inst.setOpcode(ARM::RFEDA_UPD);
2470 case ARM::LDMDB:
2471 Inst.setOpcode(ARM::RFEDB);
2473 case ARM::LDMDB_UPD:
2474 Inst.setOpcode(ARM::RFEDB_UPD);
2476 case ARM::LDMIA:
2477 Inst.setOpcode(ARM::RFEIA);
2479 case ARM::LDMIA_UPD:
2480 Inst.setOpcode(ARM::RFEIA_UPD);
2482 case ARM::LDMIB:
2483 Inst.setOpcode(ARM::RFEIB);
2485 case ARM::LDMIB_UPD:
2486 Inst.setOpcode(ARM::RFEIB_UPD);
2488 case ARM::STMDA:
2489 Inst.setOpcode(ARM::SRSDA);
2491 case ARM::STMDA_UPD:
2492 Inst.setOpcode(ARM::SRSDA_UPD);
2494 case ARM::STMDB:
2495 Inst.setOpcode(ARM::SRSDB);
2497 case ARM::STMDB_UPD:
2498 Inst.setOpcode(ARM::SRSDB_UPD);
2500 case ARM::STMIA:
2501 Inst.setOpcode(ARM::SRSIA);
2503 case ARM::STMIA_UPD:
2504 Inst.setOpcode(ARM::SRSIA_UPD);
2506 case ARM::STMIB:
2507 Inst.setOpcode(ARM::SRSIB);
2509 case ARM::STMIB_UPD:
2510 Inst.setOpcode(ARM::SRSIB_UPD);
2561 if (imm8 == 0x10 && pred != 0xe && ((FeatureBits[ARM::FeatureRAS]) != 0))
2592 Inst.setOpcode(ARM::CPS3p);
2597 Inst.setOpcode(ARM::CPS2p);
2602 Inst.setOpcode(ARM::CPS1p);
2607 Inst.setOpcode(ARM::CPS1p);
2633 Inst.setOpcode(ARM::t2CPS3p);
2638 Inst.setOpcode(ARM::t2CPS2p);
2643 Inst.setOpcode(ARM::t2CPS1p);
2651 Inst.setOpcode(ARM::t2HINT);
2663 unsigned Opcode = ARM::t2HINT;
2666 Opcode = ARM::t2PACBTI;
2668 Opcode = ARM::t2PAC;
2670 Opcode = ARM::t2AUT;
2672 Opcode = ARM::t2BTI;
2676 if (Opcode == ARM::t2HINT) {
2696 if (Inst.getOpcode() == ARM::t2MOVTi16)
2720 if (Inst.getOpcode() == ARM::MOVTi16)
2797 if (!FeatureBits[ARM::HasV8_1aOps] ||
2798 !FeatureBits[ARM::HasV8Ops])
2810 Inst.setOpcode(ARM::SETPAN);
2921 Inst.setOpcode(ARM::BLXi);
2935 if (Inst.getOpcode() != ARM::BL)
2974 case ARM::VLD1q16: case ARM::VLD1q32: case ARM::VLD1q64: case ARM::VLD1q8:
2975 case ARM::VLD1q16wb_fixed: case ARM::VLD1q16wb_register:
2976 case ARM::VLD1q32wb_fixed: case ARM::VLD1q32wb_register:
2977 case ARM::VLD1q64wb_fixed: case ARM::VLD1q64wb_register:
2978 case ARM::VLD1q8wb_fixed: case ARM::VLD1q8wb_register:
2979 case ARM::VLD2d16: case ARM::VLD2d32: case ARM::VLD2d8:
2980 case ARM::VLD2d16wb_fixed: case ARM::VLD2d16wb_register:
2981 case ARM::VLD2d32wb_fixed: case ARM::VLD2d32wb_register:
2982 case ARM::VLD2d8wb_fixed: case ARM::VLD2d8wb_register:
2986 case ARM::VLD2b16:
2987 case ARM::VLD2b32:
2988 case ARM::VLD2b8:
2989 case ARM::VLD2b16wb_fixed:
2990 case ARM::VLD2b16wb_register:
2991 case ARM::VLD2b32wb_fixed:
2992 case ARM::VLD2b32wb_register:
2993 case ARM::VLD2b8wb_fixed:
2994 case ARM::VLD2b8wb_register:
3005 case ARM::VLD3d8:
3006 case ARM::VLD3d16:
3007 case ARM::VLD3d32:
3008 case ARM::VLD3d8_UPD:
3009 case ARM::VLD3d16_UPD:
3010 case ARM::VLD3d32_UPD:
3011 case ARM::VLD4d8:
3012 case ARM::VLD4d16:
3013 case ARM::VLD4d32:
3014 case ARM::VLD4d8_UPD:
3015 case ARM::VLD4d16_UPD:
3016 case ARM::VLD4d32_UPD:
3020 case ARM::VLD3q8:
3021 case ARM::VLD3q16:
3022 case ARM::VLD3q32:
3023 case ARM::VLD3q8_UPD:
3024 case ARM::VLD3q16_UPD:
3025 case ARM::VLD3q32_UPD:
3026 case ARM::VLD4q8:
3027 case ARM::VLD4q16:
3028 case ARM::VLD4q32:
3029 case ARM::VLD4q8_UPD:
3030 case ARM::VLD4q16_UPD:
3031 case ARM::VLD4q32_UPD:
3041 case ARM::VLD3d8:
3042 case ARM::VLD3d16:
3043 case ARM::VLD3d32:
3044 case ARM::VLD3d8_UPD:
3045 case ARM::VLD3d16_UPD:
3046 case ARM::VLD3d32_UPD:
3047 case ARM::VLD4d8:
3048 case ARM::VLD4d16:
3049 case ARM::VLD4d32:
3050 case ARM::VLD4d8_UPD:
3051 case ARM::VLD4d16_UPD:
3052 case ARM::VLD4d32_UPD:
3056 case ARM::VLD3q8:
3057 case ARM::VLD3q16:
3058 case ARM::VLD3q32:
3059 case ARM::VLD3q8_UPD:
3060 case ARM::VLD3q16_UPD:
3061 case ARM::VLD3q32_UPD:
3062 case ARM::VLD4q8:
3063 case ARM::VLD4q16:
3064 case ARM::VLD4q32:
3065 case ARM::VLD4q8_UPD:
3066 case ARM::VLD4q16_UPD:
3067 case ARM::VLD4q32_UPD:
3077 case ARM::VLD4d8:
3078 case ARM::VLD4d16:
3079 case ARM::VLD4d32:
3080 case ARM::VLD4d8_UPD:
3081 case ARM::VLD4d16_UPD:
3082 case ARM::VLD4d32_UPD:
3086 case ARM::VLD4q8:
3087 case ARM::VLD4q16:
3088 case ARM::VLD4q32:
3089 case ARM::VLD4q8_UPD:
3090 case ARM::VLD4q16_UPD:
3091 case ARM::VLD4q32_UPD:
3101 case ARM::VLD1d8wb_fixed:
3102 case ARM::VLD1d16wb_fixed:
3103 case ARM::VLD1d32wb_fixed:
3104 case ARM::VLD1d64wb_fixed:
3105 case ARM::VLD1d8wb_register:
3106 case ARM::VLD1d16wb_register:
3107 case ARM::VLD1d32wb_register:
3108 case ARM::VLD1d64wb_register:
3109 case ARM::VLD1q8wb_fixed:
3110 case ARM::VLD1q16wb_fixed:
3111 case ARM::VLD1q32wb_fixed:
3112 case ARM::VLD1q64wb_fixed:
3113 case ARM::VLD1q8wb_register:
3114 case ARM::VLD1q16wb_register:
3115 case ARM::VLD1q32wb_register:
3116 case ARM::VLD1q64wb_register:
3117 case ARM::VLD1d8Twb_fixed:
3118 case ARM::VLD1d8Twb_register:
3119 case ARM::VLD1d16Twb_fixed:
3120 case ARM::VLD1d16Twb_register:
3121 case ARM::VLD1d32Twb_fixed:
3122 case ARM::VLD1d32Twb_register:
3123 case ARM::VLD1d64Twb_fixed:
3124 case ARM::VLD1d64Twb_register:
3125 case ARM::VLD1d8Qwb_fixed:
3126 case ARM::VLD1d8Qwb_register:
3127 case ARM::VLD1d16Qwb_fixed:
3128 case ARM::VLD1d16Qwb_register:
3129 case ARM::VLD1d32Qwb_fixed:
3130 case ARM::VLD1d32Qwb_register:
3131 case ARM::VLD1d64Qwb_fixed:
3132 case ARM::VLD1d64Qwb_register:
3133 case ARM::VLD2d8wb_fixed:
3134 case ARM::VLD2d16wb_fixed:
3135 case ARM::VLD2d32wb_fixed:
3136 case ARM::VLD2q8wb_fixed:
3137 case ARM::VLD2q16wb_fixed:
3138 case ARM::VLD2q32wb_fixed:
3139 case ARM::VLD2d8wb_register:
3140 case ARM::VLD2d16wb_register:
3141 case ARM::VLD2d32wb_register:
3142 case ARM::VLD2q8wb_register:
3143 case ARM::VLD2q16wb_register:
3144 case ARM::VLD2q32wb_register:
3145 case ARM::VLD2b8wb_fixed:
3146 case ARM::VLD2b16wb_fixed:
3147 case ARM::VLD2b32wb_fixed:
3148 case ARM::VLD2b8wb_register:
3149 case ARM::VLD2b16wb_register:
3150 case ARM::VLD2b32wb_register:
3153 case ARM::VLD3d8_UPD:
3154 case ARM::VLD3d16_UPD:
3155 case ARM::VLD3d32_UPD:
3156 case ARM::VLD3q8_UPD:
3157 case ARM::VLD3q16_UPD:
3158 case ARM::VLD3q32_UPD:
3159 case ARM::VLD4d8_UPD:
3160 case ARM::VLD4d16_UPD:
3161 case ARM::VLD4d32_UPD:
3162 case ARM::VLD4q8_UPD:
3163 case ARM::VLD4q16_UPD:
3164 case ARM::VLD4q32_UPD:
3191 case ARM::VLD1d8wb_fixed:
3192 case ARM::VLD1d16wb_fixed:
3193 case ARM::VLD1d32wb_fixed:
3194 case ARM::VLD1d64wb_fixed:
3195 case ARM::VLD1d8Twb_fixed:
3196 case ARM::VLD1d16Twb_fixed:
3197 case ARM::VLD1d32Twb_fixed:
3198 case ARM::VLD1d64Twb_fixed:
3199 case ARM::VLD1d8Qwb_fixed:
3200 case ARM::VLD1d16Qwb_fixed:
3201 case ARM::VLD1d32Qwb_fixed:
3202 case ARM::VLD1d64Qwb_fixed:
3203 case ARM::VLD1d8wb_register:
3204 case ARM::VLD1d16wb_register:
3205 case ARM::VLD1d32wb_register:
3206 case ARM::VLD1d64wb_register:
3207 case ARM::VLD1q8wb_fixed:
3208 case ARM::VLD1q16wb_fixed:
3209 case ARM::VLD1q32wb_fixed:
3210 case ARM::VLD1q64wb_fixed:
3211 case ARM::VLD1q8wb_register:
3212 case ARM::VLD1q16wb_register:
3213 case ARM::VLD1q32wb_register:
3214 case ARM::VLD1q64wb_register:
3222 case ARM::VLD2d8wb_fixed:
3223 case ARM::VLD2d16wb_fixed:
3224 case ARM::VLD2d32wb_fixed:
3225 case ARM::VLD2b8wb_fixed:
3226 case ARM::VLD2b16wb_fixed:
3227 case ARM::VLD2b32wb_fixed:
3228 case ARM::VLD2q8wb_fixed:
3229 case ARM::VLD2q16wb_fixed:
3230 case ARM::VLD2q32wb_fixed:
3306 case ARM::VST1d8wb_fixed:
3307 case ARM::VST1d16wb_fixed:
3308 case ARM::VST1d32wb_fixed:
3309 case ARM::VST1d64wb_fixed:
3310 case ARM::VST1d8wb_register:
3311 case ARM::VST1d16wb_register:
3312 case ARM::VST1d32wb_register:
3313 case ARM::VST1d64wb_register:
3314 case ARM::VST1q8wb_fixed:
3315 case ARM::VST1q16wb_fixed:
3316 case ARM::VST1q32wb_fixed:
3317 case ARM::VST1q64wb_fixed:
3318 case ARM::VST1q8wb_register:
3319 case ARM::VST1q16wb_register:
3320 case ARM::VST1q32wb_register:
3321 case ARM::VST1q64wb_register:
3322 case ARM::VST1d8Twb_fixed:
3323 case ARM::VST1d16Twb_fixed:
3324 case ARM::VST1d32Twb_fixed:
3325 case ARM::VST1d64Twb_fixed:
3326 case ARM::VST1d8Twb_register:
3327 case ARM::VST1d16Twb_register:
3328 case ARM::VST1d32Twb_register:
3329 case ARM::VST1d64Twb_register:
3330 case ARM::VST1d8Qwb_fixed:
3331 case ARM::VST1d16Qwb_fixed:
3332 case ARM::VST1d32Qwb_fixed:
3333 case ARM::VST1d64Qwb_fixed:
3334 case ARM::VST1d8Qwb_register:
3335 case ARM::VST1d16Qwb_register:
3336 case ARM::VST1d32Qwb_register:
3337 case ARM::VST1d64Qwb_register:
3338 case ARM::VST2d8wb_fixed:
3339 case ARM::VST2d16wb_fixed:
3340 case ARM::VST2d32wb_fixed:
3341 case ARM::VST2d8wb_register:
3342 case ARM::VST2d16wb_register:
3343 case ARM::VST2d32wb_register:
3344 case ARM::VST2q8wb_fixed:
3345 case ARM::VST2q16wb_fixed:
3346 case ARM::VST2q32wb_fixed:
3347 case ARM::VST2q8wb_register:
3348 case ARM::VST2q16wb_register:
3349 case ARM::VST2q32wb_register:
3350 case ARM::VST2b8wb_fixed:
3351 case ARM::VST2b16wb_fixed:
3352 case ARM::VST2b32wb_fixed:
3353 case ARM::VST2b8wb_register:
3354 case ARM::VST2b16wb_register:
3355 case ARM::VST2b32wb_register:
3360 case ARM::VST3d8_UPD:
3361 case ARM::VST3d16_UPD:
3362 case ARM::VST3d32_UPD:
3363 case ARM::VST3q8_UPD:
3364 case ARM::VST3q16_UPD:
3365 case ARM::VST3q32_UPD:
3366 case ARM::VST4d8_UPD:
3367 case ARM::VST4d16_UPD:
3368 case ARM::VST4d32_UPD:
3369 case ARM::VST4q8_UPD:
3370 case ARM::VST4q16_UPD:
3371 case ARM::VST4q32_UPD:
3393 case ARM::VST1d8wb_fixed:
3394 case ARM::VST1d16wb_fixed:
3395 case ARM::VST1d32wb_fixed:
3396 case ARM::VST1d64wb_fixed:
3397 case ARM::VST1q8wb_fixed:
3398 case ARM::VST1q16wb_fixed:
3399 case ARM::VST1q32wb_fixed:
3400 case ARM::VST1q64wb_fixed:
3401 case ARM::VST1d8Twb_fixed:
3402 case ARM::VST1d16Twb_fixed:
3403 case ARM::VST1d32Twb_fixed:
3404 case ARM::VST1d64Twb_fixed:
3405 case ARM::VST1d8Qwb_fixed:
3406 case ARM::VST1d16Qwb_fixed:
3407 case ARM::VST1d32Qwb_fixed:
3408 case ARM::VST1d64Qwb_fixed:
3409 case ARM::VST2d8wb_fixed:
3410 case ARM::VST2d16wb_fixed:
3411 case ARM::VST2d32wb_fixed:
3412 case ARM::VST2q8wb_fixed:
3413 case ARM::VST2q16wb_fixed:
3414 case ARM::VST2q32wb_fixed:
3415 case ARM::VST2b8wb_fixed:
3416 case ARM::VST2b16wb_fixed:
3417 case ARM::VST2b32wb_fixed:
3423 case ARM::VST1q16:
3424 case ARM::VST1q32:
3425 case ARM::VST1q64:
3426 case ARM::VST1q8:
3427 case ARM::VST1q16wb_fixed:
3428 case ARM::VST1q16wb_register:
3429 case ARM::VST1q32wb_fixed:
3430 case ARM::VST1q32wb_register:
3431 case ARM::VST1q64wb_fixed:
3432 case ARM::VST1q64wb_register:
3433 case ARM::VST1q8wb_fixed:
3434 case ARM::VST1q8wb_register:
3435 case ARM::VST2d16:
3436 case ARM::VST2d32:
3437 case ARM::VST2d8:
3438 case ARM::VST2d16wb_fixed:
3439 case ARM::VST2d16wb_register:
3440 case ARM::VST2d32wb_fixed:
3441 case ARM::VST2d32wb_register:
3442 case ARM::VST2d8wb_fixed:
3443 case ARM::VST2d8wb_register:
3447 case ARM::VST2b16:
3448 case ARM::VST2b32:
3449 case ARM::VST2b8:
3450 case ARM::VST2b16wb_fixed:
3451 case ARM::VST2b16wb_register:
3452 case ARM::VST2b32wb_fixed:
3453 case ARM::VST2b32wb_register:
3454 case ARM::VST2b8wb_fixed:
3455 case ARM::VST2b8wb_register:
3466 case ARM::VST3d8:
3467 case ARM::VST3d16:
3468 case ARM::VST3d32:
3469 case ARM::VST3d8_UPD:
3470 case ARM::VST3d16_UPD:
3471 case ARM::VST3d32_UPD:
3472 case ARM::VST4d8:
3473 case ARM::VST4d16:
3474 case ARM::VST4d32:
3475 case ARM::VST4d8_UPD:
3476 case ARM::VST4d16_UPD:
3477 case ARM::VST4d32_UPD:
3481 case ARM::VST3q8:
3482 case ARM::VST3q16:
3483 case ARM::VST3q32:
3484 case ARM::VST3q8_UPD:
3485 case ARM::VST3q16_UPD:
3486 case ARM::VST3q32_UPD:
3487 case ARM::VST4q8:
3488 case ARM::VST4q16:
3489 case ARM::VST4q32:
3490 case ARM::VST4q8_UPD:
3491 case ARM::VST4q16_UPD:
3492 case ARM::VST4q32_UPD:
3502 case ARM::VST3d8:
3503 case ARM::VST3d16:
3504 case ARM::VST3d32:
3505 case ARM::VST3d8_UPD:
3506 case ARM::VST3d16_UPD:
3507 case ARM::VST3d32_UPD:
3508 case ARM::VST4d8:
3509 case ARM::VST4d16:
3510 case ARM::VST4d32:
3511 case ARM::VST4d8_UPD:
3512 case ARM::VST4d16_UPD:
3513 case ARM::VST4d32_UPD:
3517 case ARM::VST3q8:
3518 case ARM::VST3q16:
3519 case ARM::VST3q32:
3520 case ARM::VST3q8_UPD:
3521 case ARM::VST3q16_UPD:
3522 case ARM::VST3q32_UPD:
3523 case ARM::VST4q8:
3524 case ARM::VST4q16:
3525 case ARM::VST4q32:
3526 case ARM::VST4q8_UPD:
3527 case ARM::VST4q16_UPD:
3528 case ARM::VST4q32_UPD:
3538 case ARM::VST4d8:
3539 case ARM::VST4d16:
3540 case ARM::VST4d32:
3541 case ARM::VST4d8_UPD:
3542 case ARM::VST4d16_UPD:
3543 case ARM::VST4d32_UPD:
3547 case ARM::VST4q8:
3548 case ARM::VST4q16:
3549 case ARM::VST4q32:
3550 case ARM::VST4q8_UPD:
3551 case ARM::VST4q16_UPD:
3552 case ARM::VST4q32_UPD:
3580 case ARM::VLD1DUPq16: case ARM::VLD1DUPq32: case ARM::VLD1DUPq8:
3581 case ARM::VLD1DUPq16wb_fixed: case ARM::VLD1DUPq16wb_register:
3582 case ARM::VLD1DUPq32wb_fixed: case ARM::VLD1DUPq32wb_register:
3583 case ARM::VLD1DUPq8wb_fixed: case ARM::VLD1DUPq8wb_register:
3625 case ARM::VLD2DUPd16: case ARM::VLD2DUPd32: case ARM::VLD2DUPd8:
3626 case ARM::VLD2DUPd16wb_fixed: case ARM::VLD2DUPd16wb_register:
3627 case ARM::VLD2DUPd32wb_fixed: case ARM::VLD2DUPd32wb_register:
3628 case ARM::VLD2DUPd8wb_fixed: case ARM::VLD2DUPd8wb_register:
3632 case ARM::VLD2DUPd16x2: case ARM::VLD2DUPd32x2: case ARM::VLD2DUPd8x2:
3633 case ARM::VLD2DUPd16x2wb_fixed: case ARM::VLD2DUPd16x2wb_register:
3634 case ARM::VLD2DUPd32x2wb_fixed: case ARM::VLD2DUPd32x2wb_register:
3635 case ARM::VLD2DUPd8x2wb_fixed: case ARM::VLD2DUPd8x2wb_register:
3774 case ARM::VORRiv4i16:
3775 case ARM::VORRiv2i32:
3776 case ARM::VBICiv4i16:
3777 case ARM::VBICiv2i32:
3781 case ARM::VORRiv8i16:
3782 case ARM::VORRiv4i32:
3783 case ARM::VBICiv8i16:
3784 case ARM::VBICiv4i32:
3809 if (cmode == 0xF && Inst.getOpcode() == ARM::MVE_VMVNimmi32)
3833 Inst.addOperand(MCOperand::createReg(ARM::FPSCR_NZCV));
3844 Inst.addOperand(MCOperand::createReg(ARM::FPSCR_NZCV));
3919 case ARM::VTBL2:
3920 case ARM::VTBX2:
3949 case ARM::tADR:
3951 case ARM::tADDrSPi:
3952 Inst.addOperand(MCOperand::createReg(ARM::SP));
4032 Inst.addOperand(MCOperand::createReg(ARM::SP));
4049 case ARM::t2STRHs:
4050 case ARM::t2STRBs:
4051 case ARM::t2STRs:
4079 bool hasMP = featureBits[ARM::FeatureMP];
4080 bool hasV7Ops = featureBits[ARM::HasV7Ops];
4084 case ARM::t2LDRBs:
4085 Inst.setOpcode(ARM::t2LDRBpci);
4087 case ARM::t2LDRHs:
4088 Inst.setOpcode(ARM::t2LDRHpci);
4090 case ARM::t2LDRSHs:
4091 Inst.setOpcode(ARM::t2LDRSHpci);
4093 case ARM::t2LDRSBs:
4094 Inst.setOpcode(ARM::t2LDRSBpci);
4096 case ARM::t2LDRs:
4097 Inst.setOpcode(ARM::t2LDRpci);
4099 case ARM::t2PLDs:
4100 Inst.setOpcode(ARM::t2PLDpci);
4102 case ARM::t2PLIs:
4103 Inst.setOpcode(ARM::t2PLIpci);
4114 case ARM::t2LDRSHs:
4116 case ARM::t2LDRHs:
4117 Inst.setOpcode(ARM::t2PLDWs);
4119 case ARM::t2LDRSBs:
4120 Inst.setOpcode(ARM::t2PLIs);
4128 case ARM::t2PLDs:
4130 case ARM::t2PLIs:
4134 case ARM::t2PLDWs:
4168 bool hasMP = featureBits[ARM::FeatureMP];
4169 bool hasV7Ops = featureBits[ARM::HasV7Ops];
4173 case ARM::t2LDRi8:
4174 Inst.setOpcode(ARM::t2LDRpci);
4176 case ARM::t2LDRBi8:
4177 Inst.setOpcode(ARM::t2LDRBpci);
4179 case ARM::t2LDRSBi8:
4180 Inst.setOpcode(ARM::t2LDRSBpci);
4182 case ARM::t2LDRHi8:
4183 Inst.setOpcode(ARM::t2LDRHpci);
4185 case ARM::t2LDRSHi8:
4186 Inst.setOpcode(ARM::t2LDRSHpci);
4188 case ARM::t2PLDi8:
4189 Inst.setOpcode(ARM::t2PLDpci);
4191 case ARM::t2PLIi8:
4192 Inst.setOpcode(ARM::t2PLIpci);
4202 case ARM::t2LDRSHi8:
4204 case ARM::t2LDRHi8:
4206 Inst.setOpcode(ARM::t2PLDWi8);
4208 case ARM::t2LDRSBi8:
4209 Inst.setOpcode(ARM::t2PLIi8);
4217 case ARM::t2PLDi8:
4219 case ARM::t2PLIi8:
4223 case ARM::t2PLDWi8:
4250 bool hasMP = featureBits[ARM::FeatureMP];
4251 bool hasV7Ops = featureBits[ARM::HasV7Ops];
4255 case ARM::t2LDRi12:
4256 Inst.setOpcode(ARM::t2LDRpci);
4258 case ARM::t2LDRHi12:
4259 Inst.setOpcode(ARM::t2LDRHpci);
4261 case ARM::t2LDRSHi12:
4262 Inst.setOpcode(ARM::t2LDRSHpci);
4264 case ARM::t2LDRBi12:
4265 Inst.setOpcode(ARM::t2LDRBpci);
4267 case ARM::t2LDRSBi12:
4268 Inst.setOpcode(ARM::t2LDRSBpci);
4270 case ARM::t2PLDi12:
4271 Inst.setOpcode(ARM::t2PLDpci);
4273 case ARM::t2PLIi12:
4274 Inst.setOpcode(ARM::t2PLIpci);
4284 case ARM::t2LDRSHi12:
4286 case ARM::t2LDRHi12:
4287 Inst.setOpcode(ARM::t2PLDWi12);
4289 case ARM::t2LDRSBi12:
4290 Inst.setOpcode(ARM::t2PLIi12);
4298 case ARM::t2PLDi12:
4300 case ARM::t2PLIi12:
4304 case ARM::t2PLDWi12:
4329 case ARM::t2LDRT:
4330 Inst.setOpcode(ARM::t2LDRpci);
4332 case ARM::t2LDRBT:
4333 Inst.setOpcode(ARM::t2LDRBpci);
4335 case ARM::t2LDRHT:
4336 Inst.setOpcode(ARM::t2LDRHpci);
4338 case ARM::t2LDRSBT:
4339 Inst.setOpcode(ARM::t2LDRSBpci);
4341 case ARM::t2LDRSHT:
4342 Inst.setOpcode(ARM::t2LDRSHpci);
4369 bool hasV7Ops = featureBits[ARM::HasV7Ops];
4373 case ARM::t2LDRBpci:
4374 case ARM::t2LDRHpci:
4375 Inst.setOpcode(ARM::t2PLDpci);
4377 case ARM::t2LDRSBpci:
4378 Inst.setOpcode(ARM::t2PLIpci);
4380 case ARM::t2LDRSHpci:
4388 case ARM::t2PLDpci:
4390 case ARM::t2PLIpci:
4525 case ARM::t2STRT:
4526 case ARM::t2STRBT:
4527 case ARM::t2STRHT:
4528 case ARM::t2STRi8:
4529 case ARM::t2STRHi8:
4530 case ARM::t2STRBi8:
4540 case ARM::t2LDRT:
4541 case ARM::t2LDRBT:
4542 case ARM::t2LDRHT:
4543 case ARM::t2LDRSBT:
4544 case ARM::t2LDRSHT:
4545 case ARM::t2STRT:
4546 case ARM::t2STRBT:
4547 case ARM::t2STRHT:
4612 case ARM::t2LDR_PRE:
4613 case ARM::t2LDR_POST:
4614 Inst.setOpcode(ARM::t2LDRpci);
4616 case ARM::t2LDRB_PRE:
4617 case ARM::t2LDRB_POST:
4618 Inst.setOpcode(ARM::t2LDRBpci);
4620 case ARM::t2LDRH_PRE:
4621 case ARM::t2LDRH_POST:
4622 Inst.setOpcode(ARM::t2LDRHpci);
4624 case ARM::t2LDRSB_PRE:
4625 case ARM::t2LDRSB_POST:
4627 Inst.setOpcode(ARM::t2PLIpci);
4629 Inst.setOpcode(ARM::t2LDRSBpci);
4631 case ARM::t2LDRSH_PRE:
4632 case ARM::t2LDRSH_POST:
4633 Inst.setOpcode(ARM::t2LDRSHpci);
4670 case ARM::t2STRi12:
4671 case ARM::t2STRBi12:
4672 case ARM::t2STRHi12:
4692 Inst.addOperand(MCOperand::createReg(ARM::SP));
4693 Inst.addOperand(MCOperand::createReg(ARM::SP));
4704 if (Inst.getOpcode() == ARM::tADDrSP) {
4710 Inst.addOperand(MCOperand::createReg(ARM::SP));
4713 } else if (Inst.getOpcode() == ARM::tADDspr) {
4716 Inst.addOperand(MCOperand::createReg(ARM::SP));
4717 Inst.addOperand(MCOperand::createReg(ARM::SP));
4841 if (Rn == 13 && !FeatureBits[ARM::HasV8Ops]) S = MCDisassembler::SoftFail;
4861 Inst.setOpcode(ARM::t2DSB);
4864 Inst.setOpcode(ARM::t2DMB);
4867 Inst.setOpcode(ARM::t2ISB);
4982 if (FeatureBits[ARM::FeatureMClass]) {
5002 if (!(FeatureBits[ARM::HasV7Ops]))
5010 if (!(FeatureBits[ARM::HasV8MMainlineOps]))
5020 if (!(FeatureBits[ARM::Feature8MSecExt]))
5039 if (!(FeatureBits[ARM::FeaturePACBTI]))
5048 if (Inst.getOpcode() == ARM::t2MSR_M) {
5050 if (!(FeatureBits[ARM::HasV7Ops])) {
5064 (!(FeatureBits[ARM::FeatureDSP]) && (Mask & 1)))
5084 // ARM ARM. There are patterns, but nothing regular enough to make this logic
5965 Inst.setOpcode(ARM::t2SUBri12);
5966 Inst.addOperand(MCOperand::createReg(ARM::PC));
6016 bool hasFullFP16 = featureBits[ARM::FeatureFullFP16];
6032 Inst.setOpcode(ARM::VMOVv2f32);
6037 Inst.setOpcode(ARM::VMOVv1i64);
6039 Inst.setOpcode(ARM::VMOVv8i8);
6044 Inst.setOpcode(ARM::VMVNv2i32);
6046 Inst.setOpcode(ARM::VMOVv2i32);
6051 Inst.setOpcode(ARM::VMVNv2i32);
6053 Inst.setOpcode(ARM::VMOVv2i32);
6075 bool hasFullFP16 = featureBits[ARM::FeatureFullFP16];
6091 Inst.setOpcode(ARM::VMOVv4f32);
6096 Inst.setOpcode(ARM::VMOVv2i64);
6098 Inst.setOpcode(ARM::VMOVv16i8);
6103 Inst.setOpcode(ARM::VMVNv4i32);
6105 Inst.setOpcode(ARM::VMOVv4i32);
6110 Inst.setOpcode(ARM::VMVNv4i32);
6112 Inst.setOpcode(ARM::VMOVv4i32);
6217 if (Inst.getOpcode() == ARM::MRRC2) {
6225 if (Inst.getOpcode() == ARM::MCRR2) {
6246 case ARM::VMSR_FPSCR_NZCVQC:
6247 Inst.addOperand(MCOperand::createReg(ARM::FPSCR_NZCV));
6249 case ARM::VMSR_P0:
6250 Inst.addOperand(MCOperand::createReg(ARM::VPR));
6254 if (Inst.getOpcode() != ARM::FMSTAT) {
6257 if (featureBits[ARM::ModeThumb] && !featureBits[ARM::HasV8Ops]) {
6267 case ARM::VMRS_FPSCR_NZCVQC:
6268 Inst.addOperand(MCOperand::createReg(ARM::FPSCR_NZCV));
6270 case ARM::VMRS_P0:
6271 Inst.addOperand(MCOperand::createReg(ARM::VPR));
6275 if (featureBits[ARM::ModeThumb]) {
6332 if (Inst.getOpcode() == ARM::MVE_LCTP)
6338 case ARM::t2LEUpdate:
6339 case ARM::MVE_LETP:
6340 Inst.addOperand(MCOperand::createReg(ARM::LR));
6341 Inst.addOperand(MCOperand::createReg(ARM::LR));
6343 case ARM::t2LE:
6348 case ARM::t2WLS:
6349 case ARM::MVE_WLSTP_8:
6350 case ARM::MVE_WLSTP_16:
6351 case ARM::MVE_WLSTP_32:
6352 case ARM::MVE_WLSTP_64:
6353 Inst.addOperand(MCOperand::createReg(ARM::LR));
6361 case ARM::t2DLS:
6362 case ARM::MVE_DLSTP_8:
6363 case ARM::MVE_DLSTP_16:
6364 case ARM::MVE_DLSTP_32:
6365 case ARM::MVE_DLSTP_64:
6377 Inst.setOpcode(ARM::MVE_LCTP);
6379 Inst.addOperand(MCOperand::createReg(ARM::LR));
6430 Inst.addOperand(MCOperand::createReg(ARM::APSR_NZCV));
6449 if (Inst.getOpcode() == ARM::VSCCLRMD) {
6464 Inst.addOperand(MCOperand::createReg(ARM::VPR));
6481 ARM::Q0_Q1, ARM::Q1_Q2, ARM::Q2_Q3, ARM::Q3_Q4,
6482 ARM::Q4_Q5, ARM::Q5_Q6, ARM::Q6_Q7
6497 ARM::Q0_Q1_Q2_Q3, ARM::Q1_Q2_Q3_Q4, ARM::Q2_Q3_Q4_Q5,
6498 ARM::Q3_Q4_Q5_Q6, ARM::Q4_Q5_Q6_Q7
6642 case ARM::MVE_VCVTf16s16_fix:
6643 case ARM::MVE_VCVTs16f16_fix:
6644 case ARM::MVE_VCVTf16u16_fix:
6645 case ARM::MVE_VCVTu16f16_fix:
6649 case ARM::MVE_VCVTf32s32_fix:
6650 case ARM::MVE_VCVTs32f32_fix:
6651 case ARM::MVE_VCVTf32u32_fix:
6652 case ARM::MVE_VCVTu32f32_fix:
6665 case ARM::VSTR_P0_off:
6666 case ARM::VSTR_P0_pre:
6667 case ARM::VSTR_P0_post:
6668 case ARM::VLDR_P0_off:
6669 case ARM::VLDR_P0_pre:
6670 case ARM::VLDR_P0_post:
6671 return ARM::P0;
6682 case ARM::VSTR_FPSCR_pre:
6683 case ARM::VSTR_FPSCR_NZCVQC_pre:
6684 case ARM::VLDR_FPSCR_pre:
6685 case ARM::VLDR_FPSCR_NZCVQC_pre:
6686 case ARM::VSTR_FPSCR_off:
6687 case ARM::VSTR_FPSCR_NZCVQC_off:
6688 case ARM::VLDR_FPSCR_off:
6689 case ARM::VLDR_FPSCR_NZCVQC_off:
6690 case ARM::VSTR_FPSCR_post:
6691 case ARM::VSTR_FPSCR_NZCVQC_post:
6692 case ARM::VLDR_FPSCR_post:
6693 case ARM::VLDR_FPSCR_NZCVQC_post:
6697 if (!featureBits[ARM::HasMVEIntegerOps] && !featureBits[ARM::FeatureVFP2])
6863 case ARM::MVE_ASRLr:
6864 case ARM::MVE_SQRSHRL:
6865 Inst.setOpcode(ARM::MVE_SQRSHR);
6867 case ARM::MVE_LSLLr:
6868 case ARM::MVE_UQRSHLL:
6869 Inst.setOpcode(ARM::MVE_UQRSHL);
6915 if (Inst.getOpcode() == ARM::MVE_SQRSHRL ||
6916 Inst.getOpcode() == ARM::MVE_UQRSHLL) {
6949 Inst.addOperand(MCOperand::createReg(ARM::VPR));
6986 Inst.addOperand(MCOperand::createReg(ARM::VPR));
6997 Inst.addOperand(MCOperand::createReg(ARM::VPR));
6998 Inst.addOperand(MCOperand::createReg(ARM::VPR));
7024 Inst.setOpcode(sign1 ? ARM::t2SUBspImm12 : ARM::t2ADDspImm12);
7027 Inst.setOpcode(sign1 ? ARM::t2SUBspImm : ARM::t2ADDspImm);