Lines Matching full:arm
9 /// This file implements the targeting of the RegisterBankInfo class for ARM.
30 namespace ARM {
130 } // end namespace arm
137 // (ARM::RegBanks) is unique in the compiler. At some point, it
142 const RegisterBank &RBGPR = getRegBank(ARM::GPRRegBankID);
144 assert(&ARM::GPRRegBank == &RBGPR && "The order in RegBanks is messed up");
147 assert(RBGPR.covers(*TRI.getRegClass(ARM::GPRRegClassID)) &&
149 assert(RBGPR.covers(*TRI.getRegClass(ARM::GPRwithAPSRRegClassID)) &&
151 assert(RBGPR.covers(*TRI.getRegClass(ARM::GPRnopcRegClassID)) &&
153 assert(RBGPR.covers(*TRI.getRegClass(ARM::rGPRRegClassID)) &&
155 assert(RBGPR.covers(*TRI.getRegClass(ARM::tGPRRegClassID)) &&
157 assert(RBGPR.covers(*TRI.getRegClass(ARM::tcGPRRegClassID)) &&
159 assert(RBGPR.covers(*TRI.getRegClass(ARM::tGPROdd_and_tcGPRRegClassID)) &&
165 ARM::checkPartialMappings();
166 ARM::checkValueMappings();
176 using namespace ARM;
196 return getRegBank(ARM::GPRRegBankID);
203 return getRegBank(ARM::FPRRegBankID);
228 const ValueMapping *OperandsMapping = &ARM::ValueMappings[ARM::GPR3OpsIdx];
237 ? &ARM::ValueMappings[ARM::DPR3OpsIdx]
238 : &ARM::ValueMappings[ARM::GPR3OpsIdx];
259 OperandsMapping = &ARM::ValueMappings[ARM::GPR3OpsIdx];
273 ? &ARM::ValueMappings[ARM::GPR3OpsIdx]
274 : getOperandsMapping({&ARM::ValueMappings[ARM::GPR3OpsIdx],
275 &ARM::ValueMappings[ARM::DPR3OpsIdx]});
283 ? getOperandsMapping({&ARM::ValueMappings[ARM::DPR3OpsIdx],
284 &ARM::ValueMappings[ARM::GPR3OpsIdx]})
285 : &ARM::ValueMappings[ARM::GPR3OpsIdx];
295 ? &ARM::ValueMappings[ARM::DPR3OpsIdx]
296 : &ARM::ValueMappings[ARM::SPR3OpsIdx];
303 ? getOperandsMapping({&ARM::ValueMappings[ARM::DPR3OpsIdx],
304 &ARM::ValueMappings[ARM::DPR3OpsIdx],
305 &ARM::ValueMappings[ARM::DPR3OpsIdx],
306 &ARM::ValueMappings[ARM::DPR3OpsIdx]})
307 : getOperandsMapping({&ARM::ValueMappings[ARM::SPR3OpsIdx],
308 &ARM::ValueMappings[ARM::SPR3OpsIdx],
309 &ARM::ValueMappings[ARM::SPR3OpsIdx],
310 &ARM::ValueMappings[ARM::SPR3OpsIdx]});
318 getOperandsMapping({&ARM::ValueMappings[ARM::DPR3OpsIdx],
319 &ARM::ValueMappings[ARM::SPR3OpsIdx]});
327 getOperandsMapping({&ARM::ValueMappings[ARM::SPR3OpsIdx],
328 &ARM::ValueMappings[ARM::DPR3OpsIdx]});
339 ? getOperandsMapping({&ARM::ValueMappings[ARM::GPR3OpsIdx],
340 &ARM::ValueMappings[ARM::DPR3OpsIdx]})
341 : getOperandsMapping({&ARM::ValueMappings[ARM::GPR3OpsIdx],
342 &ARM::ValueMappings[ARM::SPR3OpsIdx]});
353 ? getOperandsMapping({&ARM::ValueMappings[ARM::DPR3OpsIdx],
354 &ARM::ValueMappings[ARM::GPR3OpsIdx]})
355 : getOperandsMapping({&ARM::ValueMappings[ARM::SPR3OpsIdx],
356 &ARM::ValueMappings[ARM::GPR3OpsIdx]});
362 {Ty.getSizeInBits() == 64 ? &ARM::ValueMappings[ARM::DPR3OpsIdx]
363 : &ARM::ValueMappings[ARM::SPR3OpsIdx],
371 getOperandsMapping({&ARM::ValueMappings[ARM::GPR3OpsIdx], nullptr});
381 getOperandsMapping({&ARM::ValueMappings[ARM::GPR3OpsIdx],
382 &ARM::ValueMappings[ARM::GPR3OpsIdx],
383 &ARM::ValueMappings[ARM::GPR3OpsIdx],
384 &ARM::ValueMappings[ARM::GPR3OpsIdx]});
392 getOperandsMapping({&ARM::ValueMappings[ARM::GPR3OpsIdx], nullptr,
393 &ARM::ValueMappings[ARM::GPR3OpsIdx],
394 &ARM::ValueMappings[ARM::GPR3OpsIdx]});
410 auto FPRValueMapping = Size == 32 ? &ARM::ValueMappings[ARM::SPR3OpsIdx]
411 : &ARM::ValueMappings[ARM::DPR3OpsIdx];
413 getOperandsMapping({&ARM::ValueMappings[ARM::GPR3OpsIdx], nullptr,
427 getOperandsMapping({&ARM::ValueMappings[ARM::DPR3OpsIdx],
428 &ARM::ValueMappings[ARM::GPR3OpsIdx],
429 &ARM::ValueMappings[ARM::GPR3OpsIdx]});
442 getOperandsMapping({&ARM::ValueMappings[ARM::GPR3OpsIdx],
443 &ARM::ValueMappings[ARM::GPR3OpsIdx],
444 &ARM::ValueMappings[ARM::DPR3OpsIdx]});
452 getOperandsMapping({&ARM::ValueMappings[ARM::GPR3OpsIdx], nullptr});
461 OperandBanks[0] = Size == 64 ? &ARM::ValueMappings[ARM::DPR3OpsIdx]
462 : &ARM::ValueMappings[ARM::GPR3OpsIdx];
471 getOperandsMapping({&ARM::ValueMappings[ARM::GPR3OpsIdx], nullptr});
484 (Mapping.RegBank->getID() != ARM::FPRRegBankID ||