Lines Matching full:arm
16 #include "ARM.h"
32 #define DEBUG_TYPE "arm-pseudo"
35 VerifyARMPseudo("verify-arm-pseudo-expand", cl::Hidden,
36 cl::desc("Verify machine code after expanding ARM pseudos"));
38 #define ARM_EXPAND_PSEUDO_NAME "ARM pseudo instruction expansion pass"
171 { ARM::VLD1LNq16Pseudo, ARM::VLD1LNd16, true, false, false, EvenDblSpc, 1, 4 ,true},
172 { ARM::VLD1LNq16Pseudo_UPD, ARM::VLD1LNd16_UPD, true, true, true, EvenDblSpc, 1, 4 ,true},
173 { ARM::VLD1LNq32Pseudo, ARM::VLD1LNd32, true, false, false, EvenDblSpc, 1, 2 ,true},
174 { ARM::VLD1LNq32Pseudo_UPD, ARM::VLD1LNd32_UPD, true, true, true, EvenDblSpc, 1, 2 ,true},
175 { ARM::VLD1LNq8Pseudo, ARM::VLD1LNd8, true, false, false, EvenDblSpc, 1, 8 ,true},
176 { ARM::VLD1LNq8Pseudo_UPD, ARM::VLD1LNd8_UPD, true, true, true, EvenDblSpc, 1, 8 ,true},
178 { ARM::VLD1d16QPseudo, ARM::VLD1d16Q, true, false, false, SingleSpc, 4, 4 ,false},
179 { ARM::VLD1d16QPseudoWB_fixed, ARM::VLD1d16Qwb_fixed, true, true, false, SingleSpc, 4, 4 ,false},
180 { ARM::VLD1d16QPseudoWB_register, ARM::VLD1d16Qwb_register, true, true, true, SingleSpc, 4, 4 ,false},
181 { ARM::VLD1d16TPseudo, ARM::VLD1d16T, true, false, false, SingleSpc, 3, 4 ,false},
182 { ARM::VLD1d16TPseudoWB_fixed, ARM::VLD1d16Twb_fixed, true, true, false, SingleSpc, 3, 4 ,false},
183 { ARM::VLD1d16TPseudoWB_register, ARM::VLD1d16Twb_register, true, true, true, SingleSpc, 3, 4 ,false},
185 { ARM::VLD1d32QPseudo, ARM::VLD1d32Q, true, false, false, SingleSpc, 4, 2 ,false},
186 { ARM::VLD1d32QPseudoWB_fixed, ARM::VLD1d32Qwb_fixed, true, true, false, SingleSpc, 4, 2 ,false},
187 { ARM::VLD1d32QPseudoWB_register, ARM::VLD1d32Qwb_register, true, true, true, SingleSpc, 4, 2 ,false},
188 { ARM::VLD1d32TPseudo, ARM::VLD1d32T, true, false, false, SingleSpc, 3, 2 ,false},
189 { ARM::VLD1d32TPseudoWB_fixed, ARM::VLD1d32Twb_fixed, true, true, false, SingleSpc, 3, 2 ,false},
190 { ARM::VLD1d32TPseudoWB_register, ARM::VLD1d32Twb_register, true, true, true, SingleSpc, 3, 2 ,false},
192 { ARM::VLD1d64QPseudo, ARM::VLD1d64Q, true, false, false, SingleSpc, 4, 1 ,false},
193 { ARM::VLD1d64QPseudoWB_fixed, ARM::VLD1d64Qwb_fixed, true, true, false, SingleSpc, 4, 1 ,false},
194 { ARM::VLD1d64QPseudoWB_register, ARM::VLD1d64Qwb_register, true, true, true, SingleSpc, 4, 1 ,false},
195 { ARM::VLD1d64TPseudo, ARM::VLD1d64T, true, false, false, SingleSpc, 3, 1 ,false},
196 { ARM::VLD1d64TPseudoWB_fixed, ARM::VLD1d64Twb_fixed, true, true, false, SingleSpc, 3, 1 ,false},
197 { ARM::VLD1d64TPseudoWB_register, ARM::VLD1d64Twb_register, true, true, true, SingleSpc, 3, 1 ,false},
199 { ARM::VLD1d8QPseudo, ARM::VLD1d8Q, true, false, false, SingleSpc, 4, 8 ,false},
200 { ARM::VLD1d8QPseudoWB_fixed, ARM::VLD1d8Qwb_fixed, true, true, false, SingleSpc, 4, 8 ,false},
201 { ARM::VLD1d8QPseudoWB_register, ARM::VLD1d8Qwb_register, true, true, true, SingleSpc, 4, 8 ,false},
202 { ARM::VLD1d8TPseudo, ARM::VLD1d8T, true, false, false, SingleSpc, 3, 8 ,false},
203 { ARM::VLD1d8TPseudoWB_fixed, ARM::VLD1d8Twb_fixed, true, true, false, SingleSpc, 3, 8 ,false},
204 { ARM::VLD1d8TPseudoWB_register, ARM::VLD1d8Twb_register, true, true, true, SingleSpc, 3, 8 ,false},
206 { ARM::VLD1q16HighQPseudo, ARM::VLD1d16Q, true, false, false, SingleHighQSpc, 4, 4 ,false},
207 { ARM::VLD1q16HighQPseudo_UPD, ARM::VLD1d16Qwb_fixed, true, true, true, SingleHighQSpc, 4, 4 ,false},
208 { ARM::VLD1q16HighTPseudo, ARM::VLD1d16T, true, false, false, SingleHighTSpc, 3, 4 ,false},
209 { ARM::VLD1q16HighTPseudo_UPD, ARM::VLD1d16Twb_fixed, true, true, true, SingleHighTSpc, 3, 4 ,false},
210 { ARM::VLD1q16LowQPseudo_UPD, ARM::VLD1d16Qwb_fixed, true, true, true, SingleLowSpc, 4, 4 ,false},
211 { ARM::VLD1q16LowTPseudo_UPD, ARM::VLD1d16Twb_fixed, true, true, true, SingleLowSpc, 3, 4 ,false},
213 { ARM::VLD1q32HighQPseudo, ARM::VLD1d32Q, true, false, false, SingleHighQSpc, 4, 2 ,false},
214 { ARM::VLD1q32HighQPseudo_UPD, ARM::VLD1d32Qwb_fixed, true, true, true, SingleHighQSpc, 4, 2 ,false},
215 { ARM::VLD1q32HighTPseudo, ARM::VLD1d32T, true, false, false, SingleHighTSpc, 3, 2 ,false},
216 { ARM::VLD1q32HighTPseudo_UPD, ARM::VLD1d32Twb_fixed, true, true, true, SingleHighTSpc, 3, 2 ,false},
217 { ARM::VLD1q32LowQPseudo_UPD, ARM::VLD1d32Qwb_fixed, true, true, true, SingleLowSpc, 4, 2 ,false},
218 { ARM::VLD1q32LowTPseudo_UPD, ARM::VLD1d32Twb_fixed, true, true, true, SingleLowSpc, 3, 2 ,false},
220 { ARM::VLD1q64HighQPseudo, ARM::VLD1d64Q, true, false, false, SingleHighQSpc, 4, 1 ,false},
221 { ARM::VLD1q64HighQPseudo_UPD, ARM::VLD1d64Qwb_fixed, true, true, true, SingleHighQSpc, 4, 1 ,false},
222 { ARM::VLD1q64HighTPseudo, ARM::VLD1d64T, true, false, false, SingleHighTSpc, 3, 1 ,false},
223 { ARM::VLD1q64HighTPseudo_UPD, ARM::VLD1d64Twb_fixed, true, true, true, SingleHighTSpc, 3, 1 ,false},
224 { ARM::VLD1q64LowQPseudo_UPD, ARM::VLD1d64Qwb_fixed, true, true, true, SingleLowSpc, 4, 1 ,false},
225 { ARM::VLD1q64LowTPseudo_UPD, ARM::VLD1d64Twb_fixed, true, true, true, SingleLowSpc, 3, 1 ,false},
227 { ARM::VLD1q8HighQPseudo, ARM::VLD1d8Q, true, false, false, SingleHighQSpc, 4, 8 ,false},
228 { ARM::VLD1q8HighQPseudo_UPD, ARM::VLD1d8Qwb_fixed, true, true, true, SingleHighQSpc, 4, 8 ,false},
229 { ARM::VLD1q8HighTPseudo, ARM::VLD1d8T, true, false, false, SingleHighTSpc, 3, 8 ,false},
230 { ARM::VLD1q8HighTPseudo_UPD, ARM::VLD1d8Twb_fixed, true, true, true, SingleHighTSpc, 3, 8 ,false},
231 { ARM::VLD1q8LowQPseudo_UPD, ARM::VLD1d8Qwb_fixed, true, true, true, SingleLowSpc, 4, 8 ,false},
232 { ARM::VLD1q8LowTPseudo_UPD, ARM::VLD1d8Twb_fixed, true, true, true, SingleLowSpc, 3, 8 ,false},
234 { ARM::VLD2DUPq16EvenPseudo, ARM::VLD2DUPd16x2, true, false, false, EvenDblSpc, 2, 4 ,false},
235 { ARM::VLD2DUPq16OddPseudo, ARM::VLD2DUPd16x2, true, false, false, OddDblSpc, 2, 4 ,false},
236 { ARM::VLD2DUPq16OddPseudoWB_fixed, ARM::VLD2DUPd16x2wb_fixed, true, true, false, OddDblSpc, 2, 4 ,false},
237 { ARM::VLD2DUPq16OddPseudoWB_register, ARM::VLD2DUPd16x2wb_register, true, true, true, OddDblSpc, 2, 4 ,false},
238 { ARM::VLD2DUPq32EvenPseudo, ARM::VLD2DUPd32x2, true, false, false, EvenDblSpc, 2, 2 ,false},
239 { ARM::VLD2DUPq32OddPseudo, ARM::VLD2DUPd32x2, true, false, false, OddDblSpc, 2, 2 ,false},
240 { ARM::VLD2DUPq32OddPseudoWB_fixed, ARM::VLD2DUPd32x2wb_fixed, true, true, false, OddDblSpc, 2, 2 ,false},
241 { ARM::VLD2DUPq32OddPseudoWB_register, ARM::VLD2DUPd32x2wb_register, true, true, true, OddDblSpc, 2, 2 ,false},
242 { ARM::VLD2DUPq8EvenPseudo, ARM::VLD2DUPd8x2, true, false, false, EvenDblSpc, 2, 8 ,false},
243 { ARM::VLD2DUPq8OddPseudo, ARM::VLD2DUPd8x2, true, false, false, OddDblSpc, 2, 8 ,false},
244 { ARM::VLD2DUPq8OddPseudoWB_fixed, ARM::VLD2DUPd8x2wb_fixed, true, true, false, OddDblSpc, 2, 8 ,false},
245 { ARM::VLD2DUPq8OddPseudoWB_register, ARM::VLD2DUPd8x2wb_register, true, true, true, OddDblSpc, 2, 8 ,false},
247 { ARM::VLD2LNd16Pseudo, ARM::VLD2LNd16, true, false, false, SingleSpc, 2, 4 ,true},
248 { ARM::VLD2LNd16Pseudo_UPD, ARM::VLD2LNd16_UPD, true, true, true, SingleSpc, 2, 4 ,true},
249 { ARM::VLD2LNd32Pseudo, ARM::VLD2LNd32, true, false, false, SingleSpc, 2, 2 ,true},
250 { ARM::VLD2LNd32Pseudo_UPD, ARM::VLD2LNd32_UPD, true, true, true, SingleSpc, 2, 2 ,true},
251 { ARM::VLD2LNd8Pseudo, ARM::VLD2LNd8, true, false, false, SingleSpc, 2, 8 ,true},
252 { ARM::VLD2LNd8Pseudo_UPD, ARM::VLD2LNd8_UPD, true, true, true, SingleSpc, 2, 8 ,true},
253 { ARM::VLD2LNq16Pseudo, ARM::VLD2LNq16, true, false, false, EvenDblSpc, 2, 4 ,true},
254 { ARM::VLD2LNq16Pseudo_UPD, ARM::VLD2LNq16_UPD, true, true, true, EvenDblSpc, 2, 4 ,true},
255 { ARM::VLD2LNq32Pseudo, ARM::VLD2LNq32, true, false, false, EvenDblSpc, 2, 2 ,true},
256 { ARM::VLD2LNq32Pseudo_UPD, ARM::VLD2LNq32_UPD, true, true, true, EvenDblSpc, 2, 2 ,true},
258 { ARM::VLD2q16Pseudo, ARM::VLD2q16, true, false, false, SingleSpc, 4, 4 ,false},
259 { ARM::VLD2q16PseudoWB_fixed, ARM::VLD2q16wb_fixed, true, true, false, SingleSpc, 4, 4 ,false},
260 { ARM::VLD2q16PseudoWB_register, ARM::VLD2q16wb_register, true, true, true, SingleSpc, 4, 4 ,false},
261 { ARM::VLD2q32Pseudo, ARM::VLD2q32, true, false, false, SingleSpc, 4, 2 ,false},
262 { ARM::VLD2q32PseudoWB_fixed, ARM::VLD2q32wb_fixed, true, true, false, SingleSpc, 4, 2 ,false},
263 { ARM::VLD2q32PseudoWB_register, ARM::VLD2q32wb_register, true, true, true, SingleSpc, 4, 2 ,false},
264 { ARM::VLD2q8Pseudo, ARM::VLD2q8, true, false, false, SingleSpc, 4, 8 ,false},
265 { ARM::VLD2q8PseudoWB_fixed, ARM::VLD2q8wb_fixed, true, true, false, SingleSpc, 4, 8 ,false},
266 { ARM::VLD2q8PseudoWB_register, ARM::VLD2q8wb_register, true, true, true, SingleSpc, 4, 8 ,false},
268 { ARM::VLD3DUPd16Pseudo, ARM::VLD3DUPd16, true, false, false, SingleSpc, 3, 4,true},
269 { ARM::VLD3DUPd16Pseudo_UPD, ARM::VLD3DUPd16_UPD, true, true, true, SingleSpc, 3, 4,true},
270 { ARM::VLD3DUPd32Pseudo, ARM::VLD3DUPd32, true, false, false, SingleSpc, 3, 2,true},
271 { ARM::VLD3DUPd32Pseudo_UPD, ARM::VLD3DUPd32_UPD, true, true, true, SingleSpc, 3, 2,true},
272 { ARM::VLD3DUPd8Pseudo, ARM::VLD3DUPd8, true, false, false, SingleSpc, 3, 8,true},
273 { ARM::VLD3DUPd8Pseudo_UPD, ARM::VLD3DUPd8_UPD, true, true, true, SingleSpc, 3, 8,true},
274 { ARM::VLD3DUPq16EvenPseudo, ARM::VLD3DUPq16, true, false, false, EvenDblSpc, 3, 4 ,true},
275 { ARM::VLD3DUPq16OddPseudo, ARM::VLD3DUPq16, true, false, false, OddDblSpc, 3, 4 ,true},
276 { ARM::VLD3DUPq16OddPseudo_UPD, ARM::VLD3DUPq16_UPD, true, true, true, OddDblSpc, 3, 4 ,true},
277 { ARM::VLD3DUPq32EvenPseudo, ARM::VLD3DUPq32, true, false, false, EvenDblSpc, 3, 2 ,true},
278 { ARM::VLD3DUPq32OddPseudo, ARM::VLD3DUPq32, true, false, false, OddDblSpc, 3, 2 ,true},
279 { ARM::VLD3DUPq32OddPseudo_UPD, ARM::VLD3DUPq32_UPD, true, true, true, OddDblSpc, 3, 2 ,true},
280 { ARM::VLD3DUPq8EvenPseudo, ARM::VLD3DUPq8, true, false, false, EvenDblSpc, 3, 8 ,true},
281 { ARM::VLD3DUPq8OddPseudo, ARM::VLD3DUPq8, true, false, false, OddDblSpc, 3, 8 ,true},
282 { ARM::VLD3DUPq8OddPseudo_UPD, ARM::VLD3DUPq8_UPD, true, true, true, OddDblSpc, 3, 8 ,true},
284 { ARM::VLD3LNd16Pseudo, ARM::VLD3LNd16, true, false, false, SingleSpc, 3, 4 ,true},
285 { ARM::VLD3LNd16Pseudo_UPD, ARM::VLD3LNd16_UPD, true, true, true, SingleSpc, 3, 4 ,true},
286 { ARM::VLD3LNd32Pseudo, ARM::VLD3LNd32, true, false, false, SingleSpc, 3, 2 ,true},
287 { ARM::VLD3LNd32Pseudo_UPD, ARM::VLD3LNd32_UPD, true, true, true, SingleSpc, 3, 2 ,true},
288 { ARM::VLD3LNd8Pseudo, ARM::VLD3LNd8, true, false, false, SingleSpc, 3, 8 ,true},
289 { ARM::VLD3LNd8Pseudo_UPD, ARM::VLD3LNd8_UPD, true, true, true, SingleSpc, 3, 8 ,true},
290 { ARM::VLD3LNq16Pseudo, ARM::VLD3LNq16, true, false, false, EvenDblSpc, 3, 4 ,true},
291 { ARM::VLD3LNq16Pseudo_UPD, ARM::VLD3LNq16_UPD, true, true, true, EvenDblSpc, 3, 4 ,true},
292 { ARM::VLD3LNq32Pseudo, ARM::VLD3LNq32, true, false, false, EvenDblSpc, 3, 2 ,true},
293 { ARM::VLD3LNq32Pseudo_UPD, ARM::VLD3LNq32_UPD, true, true, true, EvenDblSpc, 3, 2 ,true},
295 { ARM::VLD3d16Pseudo, ARM::VLD3d16, true, false, false, SingleSpc, 3, 4 ,true},
296 { ARM::VLD3d16Pseudo_UPD, ARM::VLD3d16_UPD, true, true, true, SingleSpc, 3, 4 ,true},
297 { ARM::VLD3d32Pseudo, ARM::VLD3d32, true, false, false, SingleSpc, 3, 2 ,true},
298 { ARM::VLD3d32Pseudo_UPD, ARM::VLD3d32_UPD, true, true, true, SingleSpc, 3, 2 ,true},
299 { ARM::VLD3d8Pseudo, ARM::VLD3d8, true, false, false, SingleSpc, 3, 8 ,true},
300 { ARM::VLD3d8Pseudo_UPD, ARM::VLD3d8_UPD, true, true, true, SingleSpc, 3, 8 ,true},
302 { ARM::VLD3q16Pseudo_UPD, ARM::VLD3q16_UPD, true, true, true, EvenDblSpc, 3, 4 ,true},
303 { ARM::VLD3q16oddPseudo, ARM::VLD3q16, true, false, false, OddDblSpc, 3, 4 ,true},
304 { ARM::VLD3q16oddPseudo_UPD, ARM::VLD3q16_UPD, true, true, true, OddDblSpc, 3, 4 ,true},
305 { ARM::VLD3q32Pseudo_UPD, ARM::VLD3q32_UPD, true, true, true, EvenDblSpc, 3, 2 ,true},
306 { ARM::VLD3q32oddPseudo, ARM::VLD3q32, true, false, false, OddDblSpc, 3, 2 ,true},
307 { ARM::VLD3q32oddPseudo_UPD, ARM::VLD3q32_UPD, true, true, true, OddDblSpc, 3, 2 ,true},
308 { ARM::VLD3q8Pseudo_UPD, ARM::VLD3q8_UPD, true, true, true, EvenDblSpc, 3, 8 ,true},
309 { ARM::VLD3q8oddPseudo, ARM::VLD3q8, true, false, false, OddDblSpc, 3, 8 ,true},
310 { ARM::VLD3q8oddPseudo_UPD, ARM::VLD3q8_UPD, true, true, true, OddDblSpc, 3, 8 ,true},
312 { ARM::VLD4DUPd16Pseudo, ARM::VLD4DUPd16, true, false, false, SingleSpc, 4, 4,true},
313 { ARM::VLD4DUPd16Pseudo_UPD, ARM::VLD4DUPd16_UPD, true, true, true, SingleSpc, 4, 4,true},
314 { ARM::VLD4DUPd32Pseudo, ARM::VLD4DUPd32, true, false, false, SingleSpc, 4, 2,true},
315 { ARM::VLD4DUPd32Pseudo_UPD, ARM::VLD4DUPd32_UPD, true, true, true, SingleSpc, 4, 2,true},
316 { ARM::VLD4DUPd8Pseudo, ARM::VLD4DUPd8, true, false, false, SingleSpc, 4, 8,true},
317 { ARM::VLD4DUPd8Pseudo_UPD, ARM::VLD4DUPd8_UPD, true, true, true, SingleSpc, 4, 8,true},
318 { ARM::VLD4DUPq16EvenPseudo, ARM::VLD4DUPq16, true, false, false, EvenDblSpc, 4, 4 ,true},
319 { ARM::VLD4DUPq16OddPseudo, ARM::VLD4DUPq16, true, false, false, OddDblSpc, 4, 4 ,true},
320 { ARM::VLD4DUPq16OddPseudo_UPD, ARM::VLD4DUPq16_UPD, true, true, true, OddDblSpc, 4, 4 ,true},
321 { ARM::VLD4DUPq32EvenPseudo, ARM::VLD4DUPq32, true, false, false, EvenDblSpc, 4, 2 ,true},
322 { ARM::VLD4DUPq32OddPseudo, ARM::VLD4DUPq32, true, false, false, OddDblSpc, 4, 2 ,true},
323 { ARM::VLD4DUPq32OddPseudo_UPD, ARM::VLD4DUPq32_UPD, true, true, true, OddDblSpc, 4, 2 ,true},
324 { ARM::VLD4DUPq8EvenPseudo, ARM::VLD4DUPq8, true, false, false, EvenDblSpc, 4, 8 ,true},
325 { ARM::VLD4DUPq8OddPseudo, ARM::VLD4DUPq8, true, false, false, OddDblSpc, 4, 8 ,true},
326 { ARM::VLD4DUPq8OddPseudo_UPD, ARM::VLD4DUPq8_UPD, true, true, true, OddDblSpc, 4, 8 ,true},
328 { ARM::VLD4LNd16Pseudo, ARM::VLD4LNd16, true, false, false, SingleSpc, 4, 4 ,true},
329 { ARM::VLD4LNd16Pseudo_UPD, ARM::VLD4LNd16_UPD, true, true, true, SingleSpc, 4, 4 ,true},
330 { ARM::VLD4LNd32Pseudo, ARM::VLD4LNd32, true, false, false, SingleSpc, 4, 2 ,true},
331 { ARM::VLD4LNd32Pseudo_UPD, ARM::VLD4LNd32_UPD, true, true, true, SingleSpc, 4, 2 ,true},
332 { ARM::VLD4LNd8Pseudo, ARM::VLD4LNd8, true, false, false, SingleSpc, 4, 8 ,true},
333 { ARM::VLD4LNd8Pseudo_UPD, ARM::VLD4LNd8_UPD, true, true, true, SingleSpc, 4, 8 ,true},
334 { ARM::VLD4LNq16Pseudo, ARM::VLD4LNq16, true, false, false, EvenDblSpc, 4, 4 ,true},
335 { ARM::VLD4LNq16Pseudo_UPD, ARM::VLD4LNq16_UPD, true, true, true, EvenDblSpc, 4, 4 ,true},
336 { ARM::VLD4LNq32Pseudo, ARM::VLD4LNq32, true, false, false, EvenDblSpc, 4, 2 ,true},
337 { ARM::VLD4LNq32Pseudo_UPD, ARM::VLD4LNq32_UPD, true, true, true, EvenDblSpc, 4, 2 ,true},
339 { ARM::VLD4d16Pseudo, ARM::VLD4d16, true, false, false, SingleSpc, 4, 4 ,true},
340 { ARM::VLD4d16Pseudo_UPD, ARM::VLD4d16_UPD, true, true, true, SingleSpc, 4, 4 ,true},
341 { ARM::VLD4d32Pseudo, ARM::VLD4d32, true, false, false, SingleSpc, 4, 2 ,true},
342 { ARM::VLD4d32Pseudo_UPD, ARM::VLD4d32_UPD, true, true, true, SingleSpc, 4, 2 ,true},
343 { ARM::VLD4d8Pseudo, ARM::VLD4d8, true, false, false, SingleSpc, 4, 8 ,true},
344 { ARM::VLD4d8Pseudo_UPD, ARM::VLD4d8_UPD, true, true, true, SingleSpc, 4, 8 ,true},
346 { ARM::VLD4q16Pseudo_UPD, ARM::VLD4q16_UPD, true, true, true, EvenDblSpc, 4, 4 ,true},
347 { ARM::VLD4q16oddPseudo, ARM::VLD4q16, true, false, false, OddDblSpc, 4, 4 ,true},
348 { ARM::VLD4q16oddPseudo_UPD, ARM::VLD4q16_UPD, true, true, true, OddDblSpc, 4, 4 ,true},
349 { ARM::VLD4q32Pseudo_UPD, ARM::VLD4q32_UPD, true, true, true, EvenDblSpc, 4, 2 ,true},
350 { ARM::VLD4q32oddPseudo, ARM::VLD4q32, true, false, false, OddDblSpc, 4, 2 ,true},
351 { ARM::VLD4q32oddPseudo_UPD, ARM::VLD4q32_UPD, true, true, true, OddDblSpc, 4, 2 ,true},
352 { ARM::VLD4q8Pseudo_UPD, ARM::VLD4q8_UPD, true, true, true, EvenDblSpc, 4, 8 ,true},
353 { ARM::VLD4q8oddPseudo, ARM::VLD4q8, true, false, false, OddDblSpc, 4, 8 ,true},
354 { ARM::VLD4q8oddPseudo_UPD, ARM::VLD4q8_UPD, true, true, true, OddDblSpc, 4, 8 ,true},
356 { ARM::VST1LNq16Pseudo, ARM::VST1LNd16, false, false, false, EvenDblSpc, 1, 4 ,true},
357 { ARM::VST1LNq16Pseudo_UPD, ARM::VST1LNd16_UPD, false, true, true, EvenDblSpc, 1, 4 ,true},
358 { ARM::VST1LNq32Pseudo, ARM::VST1LNd32, false, false, false, EvenDblSpc, 1, 2 ,true},
359 { ARM::VST1LNq32Pseudo_UPD, ARM::VST1LNd32_UPD, false, true, true, EvenDblSpc, 1, 2 ,true},
360 { ARM::VST1LNq8Pseudo, ARM::VST1LNd8, false, false, false, EvenDblSpc, 1, 8 ,true},
361 { ARM::VST1LNq8Pseudo_UPD, ARM::VST1LNd8_UPD, false, true, true, EvenDblSpc, 1, 8 ,true},
363 { ARM::VST1d16QPseudo, ARM::VST1d16Q, false, false, false, SingleSpc, 4, 4 ,false},
364 { ARM::VST1d16QPseudoWB_fixed, ARM::VST1d16Qwb_fixed, false, true, false, SingleSpc, 4, 4 ,false},
365 { ARM::VST1d16QPseudoWB_register, ARM::VST1d16Qwb_register, false, true, true, SingleSpc, 4, 4 ,false},
366 { ARM::VST1d16TPseudo, ARM::VST1d16T, false, false, false, SingleSpc, 3, 4 ,false},
367 { ARM::VST1d16TPseudoWB_fixed, ARM::VST1d16Twb_fixed, false, true, false, SingleSpc, 3, 4 ,false},
368 { ARM::VST1d16TPseudoWB_register, ARM::VST1d16Twb_register, false, true, true, SingleSpc, 3, 4 ,false},
370 { ARM::VST1d32QPseudo, ARM::VST1d32Q, false, false, false, SingleSpc, 4, 2 ,false},
371 { ARM::VST1d32QPseudoWB_fixed, ARM::VST1d32Qwb_fixed, false, true, false, SingleSpc, 4, 2 ,false},
372 { ARM::VST1d32QPseudoWB_register, ARM::VST1d32Qwb_register, false, true, true, SingleSpc, 4, 2 ,false},
373 { ARM::VST1d32TPseudo, ARM::VST1d32T, false, false, false, SingleSpc, 3, 2 ,false},
374 { ARM::VST1d32TPseudoWB_fixed, ARM::VST1d32Twb_fixed, false, true, false, SingleSpc, 3, 2 ,false},
375 { ARM::VST1d32TPseudoWB_register, ARM::VST1d32Twb_register, false, true, true, SingleSpc, 3, 2 ,false},
377 { ARM::VST1d64QPseudo, ARM::VST1d64Q, false, false, false, SingleSpc, 4, 1 ,false},
378 { ARM::VST1d64QPseudoWB_fixed, ARM::VST1d64Qwb_fixed, false, true, false, SingleSpc, 4, 1 ,false},
379 { ARM::VST1d64QPseudoWB_register, ARM::VST1d64Qwb_register, false, true, true, SingleSpc, 4, 1 ,false},
380 { ARM::VST1d64TPseudo, ARM::VST1d64T, false, false, false, SingleSpc, 3, 1 ,false},
381 { ARM::VST1d64TPseudoWB_fixed, ARM::VST1d64Twb_fixed, false, true, false, SingleSpc, 3, 1 ,false},
382 { ARM::VST1d64TPseudoWB_register, ARM::VST1d64Twb_register, false, true, true, SingleSpc, 3, 1 ,false},
384 { ARM::VST1d8QPseudo, ARM::VST1d8Q, false, false, false, SingleSpc, 4, 8 ,false},
385 { ARM::VST1d8QPseudoWB_fixed, ARM::VST1d8Qwb_fixed, false, true, false, SingleSpc, 4, 8 ,false},
386 { ARM::VST1d8QPseudoWB_register, ARM::VST1d8Qwb_register, false, true, true, SingleSpc, 4, 8 ,false},
387 { ARM::VST1d8TPseudo, ARM::VST1d8T, false, false, false, SingleSpc, 3, 8 ,false},
388 { ARM::VST1d8TPseudoWB_fixed, ARM::VST1d8Twb_fixed, false, true, false, SingleSpc, 3, 8 ,false},
389 { ARM::VST1d8TPseudoWB_register, ARM::VST1d8Twb_register, false, true, true, SingleSpc, 3, 8 ,false},
391 { ARM::VST1q16HighQPseudo, ARM::VST1d16Q, false, false, false, SingleHighQSpc, 4, 4 ,false},
392 { ARM::VST1q16HighQPseudo_UPD, ARM::VST1d16Qwb_fixed, false, true, true, SingleHighQSpc, 4, 8 ,false},
393 { ARM::VST1q16HighTPseudo, ARM::VST1d16T, false, false, false, SingleHighTSpc, 3, 4 ,false},
394 { ARM::VST1q16HighTPseudo_UPD, ARM::VST1d16Twb_fixed, false, true, true, SingleHighTSpc, 3, 4 ,false},
395 { ARM::VST1q16LowQPseudo_UPD, ARM::VST1d16Qwb_fixed, false, true, true, SingleLowSpc, 4, 4 ,false},
396 { ARM::VST1q16LowTPseudo_UPD, ARM::VST1d16Twb_fixed, false, true, true, SingleLowSpc, 3, 4 ,false},
398 { ARM::VST1q32HighQPseudo, ARM::VST1d32Q, false, false, false, SingleHighQSpc, 4, 2 ,false},
399 { ARM::VST1q32HighQPseudo_UPD, ARM::VST1d32Qwb_fixed, false, true, true, SingleHighQSpc, 4, 8 ,false},
400 { ARM::VST1q32HighTPseudo, ARM::VST1d32T, false, false, false, SingleHighTSpc, 3, 2 ,false},
401 { ARM::VST1q32HighTPseudo_UPD, ARM::VST1d32Twb_fixed, false, true, true, SingleHighTSpc, 3, 2 ,false},
402 { ARM::VST1q32LowQPseudo_UPD, ARM::VST1d32Qwb_fixed, false, true, true, SingleLowSpc, 4, 2 ,false},
403 { ARM::VST1q32LowTPseudo_UPD, ARM::VST1d32Twb_fixed, false, true, true, SingleLowSpc, 3, 2 ,false},
405 { ARM::VST1q64HighQPseudo, ARM::VST1d64Q, false, false, false, SingleHighQSpc, 4, 1 ,false},
406 { ARM::VST1q64HighQPseudo_UPD, ARM::VST1d64Qwb_fixed, false, true, true, SingleHighQSpc, 4, 8 ,false},
407 { ARM::VST1q64HighTPseudo, ARM::VST1d64T, false, false, false, SingleHighTSpc, 3, 1 ,false},
408 { ARM::VST1q64HighTPseudo_UPD, ARM::VST1d64Twb_fixed, false, true, true, SingleHighTSpc, 3, 1 ,false},
409 { ARM::VST1q64LowQPseudo_UPD, ARM::VST1d64Qwb_fixed, false, true, true, SingleLowSpc, 4, 1 ,false},
410 { ARM::VST1q64LowTPseudo_UPD, ARM::VST1d64Twb_fixed, false, true, true, SingleLowSpc, 3, 1 ,false},
412 { ARM::VST1q8HighQPseudo, ARM::VST1d8Q, false, false, false, SingleHighQSpc, 4, 8 ,false},
413 { ARM::VST1q8HighQPseudo_UPD, ARM::VST1d8Qwb_fixed, false, true, true, SingleHighQSpc, 4, 8 ,false},
414 { ARM::VST1q8HighTPseudo, ARM::VST1d8T, false, false, false, SingleHighTSpc, 3, 8 ,false},
415 { ARM::VST1q8HighTPseudo_UPD, ARM::VST1d8Twb_fixed, false, true, true, SingleHighTSpc, 3, 8 ,false},
416 { ARM::VST1q8LowQPseudo_UPD, ARM::VST1d8Qwb_fixed, false, true, true, SingleLowSpc, 4, 8 ,false},
417 { ARM::VST1q8LowTPseudo_UPD, ARM::VST1d8Twb_fixed, false, true, true, SingleLowSpc, 3, 8 ,false},
419 { ARM::VST2LNd16Pseudo, ARM::VST2LNd16, false, false, false, SingleSpc, 2, 4 ,true},
420 { ARM::VST2LNd16Pseudo_UPD, ARM::VST2LNd16_UPD, false, true, true, SingleSpc, 2, 4 ,true},
421 { ARM::VST2LNd32Pseudo, ARM::VST2LNd32, false, false, false, SingleSpc, 2, 2 ,true},
422 { ARM::VST2LNd32Pseudo_UPD, ARM::VST2LNd32_UPD, false, true, true, SingleSpc, 2, 2 ,true},
423 { ARM::VST2LNd8Pseudo, ARM::VST2LNd8, false, false, false, SingleSpc, 2, 8 ,true},
424 { ARM::VST2LNd8Pseudo_UPD, ARM::VST2LNd8_UPD, false, true, true, SingleSpc, 2, 8 ,true},
425 { ARM::VST2LNq16Pseudo, ARM::VST2LNq16, false, false, false, EvenDblSpc, 2, 4,true},
426 { ARM::VST2LNq16Pseudo_UPD, ARM::VST2LNq16_UPD, false, true, true, EvenDblSpc, 2, 4,true},
427 { ARM::VST2LNq32Pseudo, ARM::VST2LNq32, false, false, false, EvenDblSpc, 2, 2,true},
428 { ARM::VST2LNq32Pseudo_UPD, ARM::VST2LNq32_UPD, false, true, true, EvenDblSpc, 2, 2,true},
430 { ARM::VST2q16Pseudo, ARM::VST2q16, false, false, false, SingleSpc, 4, 4 ,false},
431 { ARM::VST2q16PseudoWB_fixed, ARM::VST2q16wb_fixed, false, true, false, SingleSpc, 4, 4 ,false},
432 { ARM::VST2q16PseudoWB_register, ARM::VST2q16wb_register, false, true, true, SingleSpc, 4, 4 ,false},
433 { ARM::VST2q32Pseudo, ARM::VST2q32, false, false, false, SingleSpc, 4, 2 ,false},
434 { ARM::VST2q32PseudoWB_fixed, ARM::VST2q32wb_fixed, false, true, false, SingleSpc, 4, 2 ,false},
435 { ARM::VST2q32PseudoWB_register, ARM::VST2q32wb_register, false, true, true, SingleSpc, 4, 2 ,false},
436 { ARM::VST2q8Pseudo, ARM::VST2q8, false, false, false, SingleSpc, 4, 8 ,false},
437 { ARM::VST2q8PseudoWB_fixed, ARM::VST2q8wb_fixed, false, true, false, SingleSpc, 4, 8 ,false},
438 { ARM::VST2q8PseudoWB_register, ARM::VST2q8wb_register, false, true, true, SingleSpc, 4, 8 ,false},
440 { ARM::VST3LNd16Pseudo, ARM::VST3LNd16, false, false, false, SingleSpc, 3, 4 ,true},
441 { ARM::VST3LNd16Pseudo_UPD, ARM::VST3LNd16_UPD, false, true, true, SingleSpc, 3, 4 ,true},
442 { ARM::VST3LNd32Pseudo, ARM::VST3LNd32, false, false, false, SingleSpc, 3, 2 ,true},
443 { ARM::VST3LNd32Pseudo_UPD, ARM::VST3LNd32_UPD, false, true, true, SingleSpc, 3, 2 ,true},
444 { ARM::VST3LNd8Pseudo, ARM::VST3LNd8, false, false, false, SingleSpc, 3, 8 ,true},
445 { ARM::VST3LNd8Pseudo_UPD, ARM::VST3LNd8_UPD, false, true, true, SingleSpc, 3, 8 ,true},
446 { ARM::VST3LNq16Pseudo, ARM::VST3LNq16, false, false, false, EvenDblSpc, 3, 4,true},
447 { ARM::VST3LNq16Pseudo_UPD, ARM::VST3LNq16_UPD, false, true, true, EvenDblSpc, 3, 4,true},
448 { ARM::VST3LNq32Pseudo, ARM::VST3LNq32, false, false, false, EvenDblSpc, 3, 2,true},
449 { ARM::VST3LNq32Pseudo_UPD, ARM::VST3LNq32_UPD, false, true, true, EvenDblSpc, 3, 2,true},
451 { ARM::VST3d16Pseudo, ARM::VST3d16, false, false, false, SingleSpc, 3, 4 ,true},
452 { ARM::VST3d16Pseudo_UPD, ARM::VST3d16_UPD, false, true, true, SingleSpc, 3, 4 ,true},
453 { ARM::VST3d32Pseudo, ARM::VST3d32, false, false, false, SingleSpc, 3, 2 ,true},
454 { ARM::VST3d32Pseudo_UPD, ARM::VST3d32_UPD, false, true, true, SingleSpc, 3, 2 ,true},
455 { ARM::VST3d8Pseudo, ARM::VST3d8, false, false, false, SingleSpc, 3, 8 ,true},
456 { ARM::VST3d8Pseudo_UPD, ARM::VST3d8_UPD, false, true, true, SingleSpc, 3, 8 ,true},
458 { ARM::VST3q16Pseudo_UPD, ARM::VST3q16_UPD, false, true, true, EvenDblSpc, 3, 4 ,true},
459 { ARM::VST3q16oddPseudo, ARM::VST3q16, false, false, false, OddDblSpc, 3, 4 ,true},
460 { ARM::VST3q16oddPseudo_UPD, ARM::VST3q16_UPD, false, true, true, OddDblSpc, 3, 4 ,true},
461 { ARM::VST3q32Pseudo_UPD, ARM::VST3q32_UPD, false, true, true, EvenDblSpc, 3, 2 ,true},
462 { ARM::VST3q32oddPseudo, ARM::VST3q32, false, false, false, OddDblSpc, 3, 2 ,true},
463 { ARM::VST3q32oddPseudo_UPD, ARM::VST3q32_UPD, false, true, true, OddDblSpc, 3, 2 ,true},
464 { ARM::VST3q8Pseudo_UPD, ARM::VST3q8_UPD, false, true, true, EvenDblSpc, 3, 8 ,true},
465 { ARM::VST3q8oddPseudo, ARM::VST3q8, false, false, false, OddDblSpc, 3, 8 ,true},
466 { ARM::VST3q8oddPseudo_UPD, ARM::VST3q8_UPD, false, true, true, OddDblSpc, 3, 8 ,true},
468 { ARM::VST4LNd16Pseudo, ARM::VST4LNd16, false, false, false, SingleSpc, 4, 4 ,true},
469 { ARM::VST4LNd16Pseudo_UPD, ARM::VST4LNd16_UPD, false, true, true, SingleSpc, 4, 4 ,true},
470 { ARM::VST4LNd32Pseudo, ARM::VST4LNd32, false, false, false, SingleSpc, 4, 2 ,true},
471 { ARM::VST4LNd32Pseudo_UPD, ARM::VST4LNd32_UPD, false, true, true, SingleSpc, 4, 2 ,true},
472 { ARM::VST4LNd8Pseudo, ARM::VST4LNd8, false, false, false, SingleSpc, 4, 8 ,true},
473 { ARM::VST4LNd8Pseudo_UPD, ARM::VST4LNd8_UPD, false, true, true, SingleSpc, 4, 8 ,true},
474 { ARM::VST4LNq16Pseudo, ARM::VST4LNq16, false, false, false, EvenDblSpc, 4, 4,true},
475 { ARM::VST4LNq16Pseudo_UPD, ARM::VST4LNq16_UPD, false, true, true, EvenDblSpc, 4, 4,true},
476 { ARM::VST4LNq32Pseudo, ARM::VST4LNq32, false, false, false, EvenDblSpc, 4, 2,true},
477 { ARM::VST4LNq32Pseudo_UPD, ARM::VST4LNq32_UPD, false, true, true, EvenDblSpc, 4, 2,true},
479 { ARM::VST4d16Pseudo, ARM::VST4d16, false, false, false, SingleSpc, 4, 4 ,true},
480 { ARM::VST4d16Pseudo_UPD, ARM::VST4d16_UPD, false, true, true, SingleSpc, 4, 4 ,true},
481 { ARM::VST4d32Pseudo, ARM::VST4d32, false, false, false, SingleSpc, 4, 2 ,true},
482 { ARM::VST4d32Pseudo_UPD, ARM::VST4d32_UPD, false, true, true, SingleSpc, 4, 2 ,true},
483 { ARM::VST4d8Pseudo, ARM::VST4d8, false, false, false, SingleSpc, 4, 8 ,true},
484 { ARM::VST4d8Pseudo_UPD, ARM::VST4d8_UPD, false, true, true, SingleSpc, 4, 8 ,true},
486 { ARM::VST4q16Pseudo_UPD, ARM::VST4q16_UPD, false, true, true, EvenDblSpc, 4, 4 ,true},
487 { ARM::VST4q16oddPseudo, ARM::VST4q16, false, false, false, OddDblSpc, 4, 4 ,true},
488 { ARM::VST4q16oddPseudo_UPD, ARM::VST4q16_UPD, false, true, true, OddDblSpc, 4, 4 ,true},
489 { ARM::VST4q32Pseudo_UPD, ARM::VST4q32_UPD, false, true, true, EvenDblSpc, 4, 2 ,true},
490 { ARM::VST4q32oddPseudo, ARM::VST4q32, false, false, false, OddDblSpc, 4, 2 ,true},
491 { ARM::VST4q32oddPseudo_UPD, ARM::VST4q32_UPD, false, true, true, OddDblSpc, 4, 2 ,true},
492 { ARM::VST4q8Pseudo_UPD, ARM::VST4q8_UPD, false, true, true, EvenDblSpc, 4, 8 ,true},
493 { ARM::VST4q8oddPseudo, ARM::VST4q8, false, false, false, OddDblSpc, 4, 8 ,true},
494 { ARM::VST4q8oddPseudo_UPD, ARM::VST4q8_UPD, false, true, true, OddDblSpc, 4, 8 ,true}
522 D0 = TRI->getSubReg(Reg, ARM::dsub_0);
523 D1 = TRI->getSubReg(Reg, ARM::dsub_1);
524 D2 = TRI->getSubReg(Reg, ARM::dsub_2);
525 D3 = TRI->getSubReg(Reg, ARM::dsub_3);
527 D0 = TRI->getSubReg(Reg, ARM::dsub_4);
528 D1 = TRI->getSubReg(Reg, ARM::dsub_5);
529 D2 = TRI->getSubReg(Reg, ARM::dsub_6);
530 D3 = TRI->getSubReg(Reg, ARM::dsub_7);
532 D0 = TRI->getSubReg(Reg, ARM::dsub_3);
533 D1 = TRI->getSubReg(Reg, ARM::dsub_4);
534 D2 = TRI->getSubReg(Reg, ARM::dsub_5);
535 D3 = TRI->getSubReg(Reg, ARM::dsub_6);
537 D0 = TRI->getSubReg(Reg, ARM::dsub_0);
538 D1 = TRI->getSubReg(Reg, ARM::dsub_2);
539 D2 = TRI->getSubReg(Reg, ARM::dsub_4);
540 D3 = TRI->getSubReg(Reg, ARM::dsub_6);
543 D0 = TRI->getSubReg(Reg, ARM::dsub_1);
544 D1 = TRI->getSubReg(Reg, ARM::dsub_3);
545 D2 = TRI->getSubReg(Reg, ARM::dsub_5);
546 D3 = TRI->getSubReg(Reg, ARM::dsub_7);
569 bool IsVLD2DUP = TableEntry->RealOpc == ARM::VLD2DUPd8x2 ||
570 TableEntry->RealOpc == ARM::VLD2DUPd16x2 ||
571 TableEntry->RealOpc == ARM::VLD2DUPd32x2 ||
572 TableEntry->RealOpc == ARM::VLD2DUPd8x2wb_fixed ||
573 TableEntry->RealOpc == ARM::VLD2DUPd16x2wb_fixed ||
574 TableEntry->RealOpc == ARM::VLD2DUPd32x2wb_fixed ||
575 TableEntry->RealOpc == ARM::VLD2DUPd8x2wb_register ||
576 TableEntry->RealOpc == ARM::VLD2DUPd16x2wb_register ||
577 TableEntry->RealOpc == ARM::VLD2DUPd32x2wb_register;
582 SubRegIndex = ARM::dsub_0;
585 SubRegIndex = ARM::dsub_1;
588 unsigned DstRegPair = TRI->getMatchingSuperReg(SubReg, ARM::dsub_0,
589 &ARM::DPairSpcRegClass);
620 if (TableEntry->RealOpc == ARM::VLD1d8Qwb_fixed ||
621 TableEntry->RealOpc == ARM::VLD1d16Qwb_fixed ||
622 TableEntry->RealOpc == ARM::VLD1d32Qwb_fixed ||
623 TableEntry->RealOpc == ARM::VLD1d64Qwb_fixed ||
624 TableEntry->RealOpc == ARM::VLD1d8Twb_fixed ||
625 TableEntry->RealOpc == ARM::VLD1d16Twb_fixed ||
626 TableEntry->RealOpc == ARM::VLD1d32Twb_fixed ||
627 TableEntry->RealOpc == ARM::VLD1d64Twb_fixed ||
628 TableEntry->RealOpc == ARM::VLD2DUPd8x2wb_fixed ||
629 TableEntry->RealOpc == ARM::VLD2DUPd16x2wb_fixed ||
630 TableEntry->RealOpc == ARM::VLD2DUPd32x2wb_fixed) {
699 if (TableEntry->RealOpc == ARM::VST1d8Qwb_fixed ||
700 TableEntry->RealOpc == ARM::VST1d16Qwb_fixed ||
701 TableEntry->RealOpc == ARM::VST1d32Qwb_fixed ||
702 TableEntry->RealOpc == ARM::VST1d64Qwb_fixed ||
703 TableEntry->RealOpc == ARM::VST1d8Twb_fixed ||
704 TableEntry->RealOpc == ARM::VST1d16Twb_fixed ||
705 TableEntry->RealOpc == ARM::VST1d32Twb_fixed ||
706 TableEntry->RealOpc == ARM::VST1d64Twb_fixed) {
877 MI.getOpcode() == ARM::MQQPRStore || MI.getOpcode() == ARM::MQQQQPRStore
878 ? ARM::VSTMDIA
879 : ARM::VLDMDIA;
890 MIB.addReg(TRI->getSubReg(SrcReg, ARM::dsub_0), Flags);
891 MIB.addReg(TRI->getSubReg(SrcReg, ARM::dsub_1), Flags);
892 MIB.addReg(TRI->getSubReg(SrcReg, ARM::dsub_2), Flags);
893 MIB.addReg(TRI->getSubReg(SrcReg, ARM::dsub_3), Flags);
894 if (MI.getOpcode() == ARM::MQQQQPRStore ||
895 MI.getOpcode() == ARM::MQQQQPRLoad) {
896 MIB.addReg(TRI->getSubReg(SrcReg, ARM::dsub_4), Flags);
897 MIB.addReg(TRI->getSubReg(SrcReg, ARM::dsub_5), Flags);
898 MIB.addReg(TRI->getSubReg(SrcReg, ARM::dsub_6), Flags);
899 MIB.addReg(TRI->getSubReg(SrcReg, ARM::dsub_7), Flags);
902 if (NewOpc == ARM::VSTMDIA)
1016 unsigned Op = PendingShift ? ARM::tADDi8 : ARM::tMOVi8;
1022 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::tLSLri), DstReg)
1038 if (Op == ARM::tADDi8)
1043 LLVM_DEBUG(dbgs() << (Op == ARM::tMOVi8 ? "To: " : "And:") << " ";
1067 bool isCC = Opcode == ARM::MOVCCi32imm || Opcode == ARM::t2MOVCCi32imm;
1074 (Opcode == ARM::MOVi32imm || Opcode == ARM::MOVCCi32imm)) {
1075 // FIXME Windows CE supports older ARM CPUs
1076 assert(!STI->isTargetWindows() && "Windows on ARM requires ARMv7+");
1083 LO16 = BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::MOVi), DstReg);
1084 HI16 = BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::ORRri))
1090 LO16 = BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::MVNi), DstReg);
1091 HI16 = BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::SUBri))
1119 if (Opcode == ARM::t2MOVi32imm || Opcode == ARM::t2MOVCCi32imm) {
1120 LO16Opc = ARM::t2MOVi16;
1121 HI16Opc = ARM::t2MOVTi16;
1123 LO16Opc = ARM::MOVi16;
1124 HI16Opc = ARM::MOVTi16;
1185 BuildMI(MBB, MBBI, DL, TII->get(ARM::t2CLRM)).add(predOps(ARMCC::AL));
1188 CLRM.addReg(ARM::APSR, RegState::Define);
1189 CLRM.addReg(ARM::CPSR, RegState::Define | RegState::Implicit);
1196 BuildMI(MBB, MBBI, DL, TII->get(ARM::tMOVr), Reg)
1201 BuildMI(MBB, MBBI, DL, TII->get(ARM::t2MSR_M))
1221 if ((Reg >= ARM::Q0 && Reg <= ARM::Q7) ||
1222 (Reg >= ARM::D0 && Reg <= ARM::D15) ||
1223 (Reg >= ARM::S0 && Reg <= ARM::S31))
1228 if (Reg >= ARM::Q0 && Reg <= ARM::Q7) {
1229 int R = Reg - ARM::Q0;
1231 } else if (Reg >= ARM::D0 && Reg <= ARM::D15) {
1232 int R = Reg - ARM::D0;
1234 } else if (Reg >= ARM::S0 && Reg <= ARM::S31) {
1235 ClearRegs[Reg - ARM::S0] = false;
1291 if (Reg == ARM::NoRegister || Reg == ARM::LR)
1297 ClearBB->addLiveIn(ARM::LR);
1298 DoneBB->addLiveIn(ARM::LR);
1301 BuildMI(MBB, MBB.end(), DL, TII->get(ARM::t2MRS_M), ARM::R12)
1305 BuildMI(MBB, MBB.end(), DL, TII->get(ARM::t2TSTri))
1306 .addReg(ARM::R12)
1310 BuildMI(MBB, MBB.end(), DL, TII->get(ARM::tBcc))
1313 .addReg(ARM::CPSR, RegState::Kill);
1320 unsigned Reg = ARM::D0 + D;
1321 BuildMI(ClearBB, DL, TII->get(ARM::VMOVDRR), Reg)
1322 .addReg(ARM::LR)
1323 .addReg(ARM::LR)
1328 unsigned Reg = ARM::S0 + D * 2;
1329 BuildMI(ClearBB, DL, TII->get(ARM::VMOVSR), Reg)
1330 .addReg(ARM::LR)
1335 unsigned Reg = ARM::S0 + D * 2 + 1;
1336 BuildMI(ClearBB, DL, TII->get(ARM::VMOVSR), Reg)
1337 .addReg(ARM::LR)
1345 BuildMI(ClearBB, DL, TII->get(ARM::VMRS), ARM::R12)
1347 BuildMI(ClearBB, DL, TII->get(ARM::t2BICri), ARM::R12)
1348 .addReg(ARM::R12)
1352 BuildMI(ClearBB, DL, TII->get(ARM::t2BICri), ARM::R12)
1353 .addReg(ARM::R12)
1357 BuildMI(ClearBB, DL, TII->get(ARM::VMSR))
1358 .addReg(ARM::R12)
1381 BuildMI(MBB, MBBI, RetI.getDebugLoc(), TII->get(ARM::VSCCLRMS))
1384 VSCCLRM.addReg(ARM::S0 + Start, RegState::Define);
1385 VSCCLRM.addReg(ARM::VPR, RegState::Define);
1392 BuildMI(MBB, MBBI, RetI.getDebugLoc(), TII->get(ARM::VSCCLRMS))
1395 VSCCLRM.addReg(ARM::S0 + Start, RegState::Define);
1396 VSCCLRM.addReg(ARM::VPR, RegState::Define);
1421 BuildMI(MBB, MBBI, DL, TII->get(ARM::tSUBspi), ARM::SP)
1422 .addReg(ARM::SP)
1432 assert(!ARM::DPRRegClass.contains(Reg) ||
1433 ARM::DPR_VFP2RegClass.contains(Reg));
1434 assert(!ARM::QPRRegClass.contains(Reg));
1435 if (ARM::DPR_VFP2RegClass.contains(Reg)) {
1442 BuildMI(MBB, MBBI, DL, TII->get(ARM::VMOVRRD))
1450 } else if (ARM::SPRRegClass.contains(Reg)) {
1456 BuildMI(MBB, MBBI, DL, TII->get(ARM::VMOVRS), SaveReg)
1474 BuildMI(MBB, MBBI, DL, TII->get(ARM::VLSTM))
1475 .addReg(ARM::SP)
1491 if (ARM::DPR_VFP2RegClass.contains(Reg))
1492 BuildMI(MBB, MBBI, DL, TII->get(ARM::VMOVDRR), Reg)
1496 else if (ARM::SPRRegClass.contains(Reg))
1497 BuildMI(MBB, MBBI, DL, TII->get(ARM::VMOVSR), Reg)
1503 if (ARM::DPR_VFP2RegClass.contains(Reg)) {
1505 BuildMI(MBB, MBBI, DL, TII->get(ARM::VLDRD), Reg)
1506 .addReg(ARM::SP)
1507 .addImm((Reg - ARM::D0) * 2)
1512 unsigned SReg0 = TRI->getSubReg(Reg, ARM::ssub_0);
1513 BuildMI(MBB, MBBI, DL, TII->get(ARM::VLDRS), SReg0)
1514 .addReg(ARM::SP)
1515 .addImm((Reg - ARM::D0) * 2)
1517 BuildMI(MBB, MBBI, DL, TII->get(ARM::VLDRS), SReg0 + 1)
1518 .addReg(ARM::SP)
1519 .addImm((Reg - ARM::D0) * 2 + 1)
1522 } else if (ARM::SPRRegClass.contains(Reg)) {
1523 BuildMI(MBB, MBBI, DL, TII->get(ARM::VLDRS), Reg)
1524 .addReg(ARM::SP)
1525 .addImm(Reg - ARM::S0)
1532 BuildMI(MBB, MBBI, DL, TII->get(ARM::tLDRspi), SpareReg)
1533 .addReg(ARM::SP)
1536 BuildMI(MBB, MBBI, DL, TII->get(ARM::t2BICri), SpareReg)
1541 BuildMI(MBB, MBBI, DL, TII->get(ARM::t2BICri), SpareReg)
1546 BuildMI(MBB, MBBI, DL, TII->get(ARM::VMSR))
1567 BuildMI(MBB, MBBI, DL, TII->get(ARM::tSUBspi), ARM::SP)
1568 .addReg(ARM::SP)
1574 BuildMI(MBB, MBBI, DL, TII->get(ARM::VLSTM))
1575 .addReg(ARM::SP)
1589 BuildMI(MBB, MBBI, DL, TII->get(ARM::VSTMSDB_UPD), ARM::SP)
1590 .addReg(ARM::SP)
1592 for (int Reg = ARM::S16; Reg <= ARM::S31; ++Reg)
1599 BuildMI(MBB, MBBI, DL, TII->get(ARM::VSTR_FPCXTS_pre), ARM::SP)
1600 .addReg(ARM::SP)
1621 unsigned ScratchReg = ARM::NoRegister;
1631 assert(!ARM::DPRRegClass.contains(Reg) ||
1632 ARM::DPR_VFP2RegClass.contains(Reg));
1633 assert(!ARM::QPRRegClass.contains(Reg));
1634 if (ARM::DPR_VFP2RegClass.contains(Reg)) {
1641 BuildMI(MBB, MBBI, DL, TII->get(ARM::VMOVRRD))
1649 } else if (ARM::SPRRegClass.contains(Reg)) {
1655 BuildMI(MBB, MBBI, DL, TII->get(ARM::VMOVRS), SaveReg)
1672 if (ARM::DPR_VFP2RegClass.contains(Reg))
1673 BuildMI(MBB, MBBI, DL, TII->get(ARM::VSTRD))
1675 .addReg(ARM::SP)
1676 .addImm((Reg - ARM::D0) * 2)
1678 else if (ARM::SPRRegClass.contains(Reg))
1679 BuildMI(MBB, MBBI, DL, TII->get(ARM::VSTRS))
1681 .addReg(ARM::SP)
1682 .addImm(Reg - ARM::S0)
1689 BuildMI(MBB, MBBI, DL, TII->get(ARM::VLLDM))
1690 .addReg(ARM::SP)
1698 Bundler.append(BuildMI(*MBB.getParent(), DL, TII->get(ARM::t2MRS_M))
1703 Bundler.append(BuildMI(*MBB.getParent(), DL, TII->get(ARM::t2TSTri))
1708 Bundler.append(BuildMI(*MBB.getParent(), DL, TII->get(ARM::t2IT))
1716 Bundler.append(BuildMI(*MBB.getParent(), DL, TII->get(ARM::VMOVS))
1717 .addReg(ARM::S0, RegState::Define)
1718 .addReg(ARM::S0, RegState::Undef)
1721 Bundler.append(BuildMI(*MBB.getParent(), DL, TII->get(ARM::INLINEASM))
1731 if (ARM::DPR_VFP2RegClass.contains(Reg))
1732 BuildMI(MBB, MBBI, DL, TII->get(ARM::VMOVDRR), Reg)
1736 else if (ARM::SPRRegClass.contains(Reg))
1737 BuildMI(MBB, MBBI, DL, TII->get(ARM::VMOVSR), Reg)
1743 BuildMI(MBB, MBBI, DL, TII->get(ARM::tADDspi), ARM::SP)
1744 .addReg(ARM::SP)
1754 if ((Reg >= ARM::Q0 && Reg <= ARM::Q7) ||
1755 (Reg >= ARM::D0 && Reg <= ARM::D15) ||
1756 (Reg >= ARM::S0 && Reg <= ARM::S31))
1767 BuildMI(MBB, MBBI, DL, TII->get(ARM::VSCCLRMS))
1769 .addReg(ARM::VPR, RegState::Define);
1773 BuildMI(MBB, MBBI, DL, TII->get(ARM::VLLDM))
1774 .addReg(ARM::SP)
1780 BuildMI(MBB, MBBI, DL, TII->get(ARM::tADDspi), ARM::SP)
1781 .addReg(ARM::SP)
1786 BuildMI(MBB, MBBI, MBBI->getDebugLoc(), TII->get(ARM::VLDR_FPCXTS_post),
1787 ARM::SP)
1788 .addReg(ARM::SP)
1794 BuildMI(MBB, MBBI, DL, TII->get(ARM::VLDMSIA_UPD), ARM::SP)
1795 .addReg(ARM::SP)
1797 for (int Reg = ARM::S16; Reg <= ARM::S31; ++Reg)
1826 assert((UxtOp == 0 || UxtOp == ARM::tUXTB || UxtOp == ARM::tUXTH) &&
1828 assert((UxtOp == 0 || ARM::tGPRRegClass.contains(DesiredReg)) &&
1858 if (LdrexOp == ARM::t2LDREX)
1862 unsigned CMPrr = IsThumb ? ARM::tCMPhir : ARM::CMPrr;
1867 unsigned Bcc = IsThumb ? ARM::tBcc : ARM::Bcc;
1871 .addReg(ARM::CPSR, RegState::Kill);
1882 if (StrexOp == ARM::t2STREX)
1887 IsThumb ? (IsThumb1Only ? ARM::tCMPi8 : ARM::t2CMPri) : ARM::CMPri;
1895 .addReg(ARM::CPSR, RegState::Kill);
1921 /// ARM's ldrexd/strexd take a consecutive register pair (represented as a
1928 Register RegLo = TRI->getSubReg(Reg.getReg(), ARM::gsub_0);
1929 Register RegHi = TRI->getSubReg(Reg.getReg(), ARM::gsub_1);
1954 Register DestLo = TRI->getSubReg(Dest.getReg(), ARM::gsub_0);
1955 Register DestHi = TRI->getSubReg(Dest.getReg(), ARM::gsub_1);
1956 Register DesiredLo = TRI->getSubReg(DesiredReg, ARM::gsub_0);
1957 Register DesiredHi = TRI->getSubReg(DesiredReg, ARM::gsub_1);
1973 unsigned LDREXD = IsThumb ? ARM::t2LDREXD : ARM::LDREXD;
1979 unsigned CMPrr = IsThumb ? ARM::tCMPhir : ARM::CMPrr;
1988 .addImm(ARMCC::EQ).addReg(ARM::CPSR, RegState::Kill);
1990 unsigned Bcc = IsThumb ? ARM::tBcc : ARM::Bcc;
1994 .addReg(ARM::CPSR, RegState::Kill);
2002 unsigned STREXD = IsThumb ? ARM::t2STREXD : ARM::STREXD;
2008 unsigned CMPri = IsThumb ? ARM::t2CMPri : ARM::CMPri;
2016 .addReg(ARM::CPSR, RegState::Kill);
2049 BuildMI(MBB, MBBI, DL, TII.get(ARM::tPUSH)).add(predOps(ARMCC::AL));
2050 for (int Reg = ARM::R4; Reg < ARM::R8; ++Reg) {
2062 for (int LoReg = ARM::R7, HiReg = ARM::R11; LoReg >= ARM::R4; --LoReg) {
2065 BuildMI(MBB, MBBI, DL, TII.get(ARM::tMOVr), LoReg)
2071 BuildMI(MBB, MBBI, DL, TII.get(ARM::tPUSH)).add(predOps(ARMCC::AL));
2072 for (int Reg = ARM::R4; Reg < ARM::R8; ++Reg) {
2081 if (JumpReg >= ARM::R4 && JumpReg <= ARM::R7) {
2082 int LoReg = JumpReg == ARM::R4 ? ARM::R5 : ARM::R4;
2083 BuildMI(MBB, MBBI, DL, TII.get(ARM::tMOVr), LoReg)
2084 .addReg(ARM::R8, LiveRegs.contains(ARM::R8) ? 0 : RegState::Undef)
2086 BuildMI(MBB, MBBI, DL, TII.get(ARM::tPUSH))
2092 BuildMI(MBB, MBBI, DL, TII.get(ARM::t2STMDB_UPD), ARM::SP)
2093 .addReg(ARM::SP)
2095 for (int Reg = ARM::R4; Reg < ARM::R12; ++Reg) {
2109 BuildMI(MBB, MBBI, DL, TII.get(ARM::tPOP)).add(predOps(ARMCC::AL));
2111 PopMIB.addReg(ARM::R4 + R, RegState::Define);
2112 BuildMI(MBB, MBBI, DL, TII.get(ARM::tMOVr), ARM::R8 + R)
2113 .addReg(ARM::R4 + R, RegState::Kill)
2117 BuildMI(MBB, MBBI, DL, TII.get(ARM::tPOP)).add(predOps(ARMCC::AL));
2119 PopMIB2.addReg(ARM::R4 + R, RegState::Define);
2122 BuildMI(MBB, MBBI, DL, TII.get(ARM::t2LDMIA_UPD), ARM::SP)
2123 .addReg(ARM::SP)
2125 for (int Reg = ARM::R4; Reg < ARM::R12; ++Reg)
2139 case ARM::VBSPd:
2140 case ARM::VBSPq: {
2144 unsigned NewOpc = Opcode == ARM::VBSPd ? ARM::VBITd : ARM::VBITq;
2154 unsigned NewOpc = Opcode == ARM::VBSPd ? ARM::VBIFd : ARM::VBIFq;
2164 unsigned NewOpc = Opcode == ARM::VBSPd ? ARM::VBSLd : ARM::VBSLq;
2175 unsigned MoveOpc = Opcode == ARM::VBSPd ? ARM::VORRd : ARM::VORRq;
2199 case ARM::TCRETURNdi:
2200 case ARM::TCRETURNri:
2201 case ARM::TCRETURNrinotr12: {
2203 if (MBBI->getOpcode() == ARM::SEH_EpilogEnd)
2205 if (MBBI->getOpcode() == ARM::SEH_Nop_Ret)
2216 if (MBBI->getOpcode() == ARM::SEH_EpilogEnd)
2218 if (MBBI->getOpcode() == ARM::SEH_Nop_Ret)
2223 if (RetOpcode == ARM::TCRETURNdi) {
2229 ? ((STI->isTargetMachO() || NeedsWinCFI) ? ARM::tTAILJMPd
2230 : ARM::tTAILJMPdND)
2231 : ARM::TAILJMPd;
2245 } else if (RetOpcode == ARM::TCRETURNri ||
2246 RetOpcode == ARM::TCRETURNrinotr12) {
2248 STI->isThumb() ? ARM::tTAILJMPr
2249 : (STI->hasV4TOps() ? ARM::TAILJMPr : ARM::TAILJMPr4);
2271 case ARM::tBXNS_RET: {
2275 BuildMI(MBB, MBBI, DebugLoc(), TII->get(ARM::t2AUT));
2282 TII->get(ARM::VLDR_FPCXTNS_post), ARM::SP)
2283 .addReg(ARM::SP)
2288 BuildMI(AfterBB, AfterBB.end(), DebugLoc(), TII->get(ARM::t2AUT));
2293 return !Op.isReg() || Op.getReg() != ARM::R12;
2297 *MBBI, {ARM::R0, ARM::R1, ARM::R2, ARM::R3, ARM::R12}, ClearRegs);
2299 ARM::LR);
2303 TII->get(ARM::tBXNS))
2304 .addReg(ARM::LR)
2311 case ARM::tBLXNS_CALL: {
2330 {ARM::R0, ARM::R1, ARM::R2, ARM::R3, ARM::R4,
2331 ARM::R5, ARM::R6, ARM::R7, ARM::R8, ARM::R9,
2332 ARM::R10, ARM::R11, ARM::R12},
2342 BuildMI(MBB, MBBI, DL, TII->get(ARM::t2BICri), JumpReg)
2351 BuildMI(MBB, MBBI, DL, TII->get(ARM::tMOVi8), ScratchReg)
2355 BuildMI(MBB, MBBI, DL, TII->get(ARM::tBIC), JumpReg)
2356 .addReg(ARM::CPSR, RegState::Define)
2367 BuildMI(MBB, MBBI, DL, TII->get(ARM::tBLXNSr))
2383 case ARM::VMOVHcc:
2384 case ARM::VMOVScc:
2385 case ARM::VMOVDcc: {
2386 unsigned newOpc = Opcode != ARM::VMOVDcc ? ARM::VMOVS : ARM::VMOVD;
2397 case ARM::t2MOVCCr:
2398 case ARM::MOVCCr: {
2399 unsigned Opc = AFI->isThumbFunction() ? ARM::t2MOVr : ARM::MOVr;
2411 case ARM::MOVCCsi: {
2412 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::MOVsi),
2424 case ARM::MOVCCsr: {
2425 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::MOVsr),
2438 case ARM::t2MOVCCi16:
2439 case ARM::MOVCCi16: {
2440 unsigned NewOpc = AFI->isThumbFunction() ? ARM::t2MOVi16 : ARM::MOVi16;
2450 case ARM::t2MOVCCi:
2451 case ARM::MOVCCi: {
2452 unsigned Opc = AFI->isThumbFunction() ? ARM::t2MOVi : ARM::MOVi;
2464 case ARM::t2MVNCCi:
2465 case ARM::MVNCCi: {
2466 unsigned Opc = AFI->isThumbFunction() ? ARM::t2MVNi : ARM::MVNi;
2478 case ARM::t2MOVCClsl:
2479 case ARM::t2MOVCClsr:
2480 case ARM::t2MOVCCasr:
2481 case ARM::t2MOVCCror: {
2484 case ARM::t2MOVCClsl: NewOpc = ARM::t2LSLri; break;
2485 case ARM::t2MOVCClsr: NewOpc = ARM::t2LSRri; break;
2486 case ARM::t2MOVCCasr: NewOpc = ARM::t2ASRri; break;
2487 case ARM::t2MOVCCror: NewOpc = ARM::t2RORri; break;
2501 case ARM::Int_eh_sjlj_dispatchsetup: {
2516 emitT2RegPlusImmediate(MBB, MBBI, MI.getDebugLoc(), ARM::R6,
2519 emitThumbRegPlusImmediate(MBB, MBBI, MI.getDebugLoc(), ARM::R6,
2522 emitARMRegPlusImmediate(MBB, MBBI, MI.getDebugLoc(), ARM::R6,
2537 ARM::t2BICri : ARM::BICri;
2538 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(bicOpc), ARM::R6)
2539 .addReg(ARM::R6, RegState::Kill)
2549 case ARM::MOVsrl_glue:
2550 case ARM::MOVsra_glue: {
2552 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::MOVsi),
2556 (Opcode == ARM::MOVsrl_glue ? ARM_AM::lsr : ARM_AM::asr), 1))
2558 .addReg(ARM::CPSR, RegState::Define);
2562 case ARM::RRX: {
2564 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::MOVsi),
2574 case ARM::tTPsoft:
2575 case ARM::TPsoft: {
2576 const bool Thumb = Opcode == ARM::tTPsoft;
2589 TII->get(Thumb ? ARM::tLDRpci : ARM::LDRi12), Reg)
2603 TII->get(Thumb ? ARM::tBL : ARM::BL));
2617 case ARM::tLDRpci_pic:
2618 case ARM::t2LDRpci_pic: {
2619 unsigned NewLdOpc = (Opcode == ARM::tLDRpci_pic)
2620 ? ARM::tLDRpci : ARM::t2LDRpci;
2628 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::tPICADD))
2637 case ARM::LDRLIT_ga_abs:
2638 case ARM::LDRLIT_ga_pcrel:
2639 case ARM::LDRLIT_ga_pcrel_ldr:
2640 case ARM::tLDRLIT_ga_abs:
2641 case ARM::t2LDRLIT_ga_pcrel:
2642 case ARM::tLDRLIT_ga_pcrel: {
2648 bool IsARM = Opcode != ARM::tLDRLIT_ga_pcrel &&
2649 Opcode != ARM::tLDRLIT_ga_abs &&
2650 Opcode != ARM::t2LDRLIT_ga_pcrel;
2652 Opcode != ARM::LDRLIT_ga_abs && Opcode != ARM::tLDRLIT_ga_abs;
2653 unsigned LDRLITOpc = IsARM ? ARM::LDRi12 : ARM::tLDRpci;
2654 if (Opcode == ARM::t2LDRLIT_ga_pcrel)
2655 LDRLITOpc = ARM::t2LDRpci;
2658 ? (Opcode == ARM::LDRLIT_ga_pcrel_ldr ? ARM::PICLDR : ARM::PICADD)
2659 : ARM::tPICADD;
2699 case ARM::MOV_ga_pcrel:
2700 case ARM::MOV_ga_pcrel_ldr:
2701 case ARM::t2MOV_ga_pcrel: {
2709 bool isARM = Opcode != ARM::t2MOV_ga_pcrel;
2710 unsigned LO16Opc = isARM ? ARM::MOVi16_ga_pcrel : ARM::t2MOVi16_ga_pcrel;
2711 unsigned HI16Opc = isARM ? ARM::MOVTi16_ga_pcrel :ARM::t2MOVTi16_ga_pcrel;
2715 ? (Opcode == ARM::MOV_ga_pcrel_ldr ? ARM::PICLDR : ARM::PICADD)
2716 : ARM::tPICADD;
2734 if (Opcode == ARM::MOV_ga_pcrel_ldr)
2742 case ARM::MOVi32imm:
2743 case ARM::MOVCCi32imm:
2744 case ARM::t2MOVi32imm:
2745 case ARM::t2MOVCCi32imm:
2749 case ARM::tMOVi32imm:
2753 case ARM::tLEApcrelJT:
2764 case ARM::SUBS_PC_LR: {
2765 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::SUBri), ARM::PC)
2766 .addReg(ARM::LR)
2770 .addReg(ARM::CPSR, RegState::Undef)
2775 case ARM::VLDMQIA: {
2776 unsigned NewOpc = ARM::VLDMDIA;
2793 Register D0 = TRI->getSubReg(DstReg, ARM::dsub_0);
2794 Register D1 = TRI->getSubReg(DstReg, ARM::dsub_1);
2806 case ARM::VSTMQIA: {
2807 unsigned NewOpc = ARM::VSTMDIA;
2825 Register D0 = TRI->getSubReg(SrcReg, ARM::dsub_0);
2826 Register D1 = TRI->getSubReg(SrcReg, ARM::dsub_1);
2839 case ARM::VLD2q8Pseudo:
2840 case ARM::VLD2q16Pseudo:
2841 case ARM::VLD2q32Pseudo:
2842 case ARM::VLD2q8PseudoWB_fixed:
2843 case ARM::VLD2q16PseudoWB_fixed:
2844 case ARM::VLD2q32PseudoWB_fixed:
2845 case ARM::VLD2q8PseudoWB_register:
2846 case ARM::VLD2q16PseudoWB_register:
2847 case ARM::VLD2q32PseudoWB_register:
2848 case ARM::VLD3d8Pseudo:
2849 case ARM::VLD3d16Pseudo:
2850 case ARM::VLD3d32Pseudo:
2851 case ARM::VLD1d8TPseudo:
2852 case ARM::VLD1d8TPseudoWB_fixed:
2853 case ARM::VLD1d8TPseudoWB_register:
2854 case ARM::VLD1d16TPseudo:
2855 case ARM::VLD1d16TPseudoWB_fixed:
2856 case ARM::VLD1d16TPseudoWB_register:
2857 case ARM::VLD1d32TPseudo:
2858 case ARM::VLD1d32TPseudoWB_fixed:
2859 case ARM::VLD1d32TPseudoWB_register:
2860 case ARM::VLD1d64TPseudo:
2861 case ARM::VLD1d64TPseudoWB_fixed:
2862 case ARM::VLD1d64TPseudoWB_register:
2863 case ARM::VLD3d8Pseudo_UPD:
2864 case ARM::VLD3d16Pseudo_UPD:
2865 case ARM::VLD3d32Pseudo_UPD:
2866 case ARM::VLD3q8Pseudo_UPD:
2867 case ARM::VLD3q16Pseudo_UPD:
2868 case ARM::VLD3q32Pseudo_UPD:
2869 case ARM::VLD3q8oddPseudo:
2870 case ARM::VLD3q16oddPseudo:
2871 case ARM::VLD3q32oddPseudo:
2872 case ARM::VLD3q8oddPseudo_UPD:
2873 case ARM::VLD3q16oddPseudo_UPD:
2874 case ARM::VLD3q32oddPseudo_UPD:
2875 case ARM::VLD4d8Pseudo:
2876 case ARM::VLD4d16Pseudo:
2877 case ARM::VLD4d32Pseudo:
2878 case ARM::VLD1d8QPseudo:
2879 case ARM::VLD1d8QPseudoWB_fixed:
2880 case ARM::VLD1d8QPseudoWB_register:
2881 case ARM::VLD1d16QPseudo:
2882 case ARM::VLD1d16QPseudoWB_fixed:
2883 case ARM::VLD1d16QPseudoWB_register:
2884 case ARM::VLD1d32QPseudo:
2885 case ARM::VLD1d32QPseudoWB_fixed:
2886 case ARM::VLD1d32QPseudoWB_register:
2887 case ARM::VLD1d64QPseudo:
2888 case ARM::VLD1d64QPseudoWB_fixed:
2889 case ARM::VLD1d64QPseudoWB_register:
2890 case ARM::VLD1q8HighQPseudo:
2891 case ARM::VLD1q8HighQPseudo_UPD:
2892 case ARM::VLD1q8LowQPseudo_UPD:
2893 case ARM::VLD1q8HighTPseudo:
2894 case ARM::VLD1q8HighTPseudo_UPD:
2895 case ARM::VLD1q8LowTPseudo_UPD:
2896 case ARM::VLD1q16HighQPseudo:
2897 case ARM::VLD1q16HighQPseudo_UPD:
2898 case ARM::VLD1q16LowQPseudo_UPD:
2899 case ARM::VLD1q16HighTPseudo:
2900 case ARM::VLD1q16HighTPseudo_UPD:
2901 case ARM::VLD1q16LowTPseudo_UPD:
2902 case ARM::VLD1q32HighQPseudo:
2903 case ARM::VLD1q32HighQPseudo_UPD:
2904 case ARM::VLD1q32LowQPseudo_UPD:
2905 case ARM::VLD1q32HighTPseudo:
2906 case ARM::VLD1q32HighTPseudo_UPD:
2907 case ARM::VLD1q32LowTPseudo_UPD:
2908 case ARM::VLD1q64HighQPseudo:
2909 case ARM::VLD1q64HighQPseudo_UPD:
2910 case ARM::VLD1q64LowQPseudo_UPD:
2911 case ARM::VLD1q64HighTPseudo:
2912 case ARM::VLD1q64HighTPseudo_UPD:
2913 case ARM::VLD1q64LowTPseudo_UPD:
2914 case ARM::VLD4d8Pseudo_UPD:
2915 case ARM::VLD4d16Pseudo_UPD:
2916 case ARM::VLD4d32Pseudo_UPD:
2917 case ARM::VLD4q8Pseudo_UPD:
2918 case ARM::VLD4q16Pseudo_UPD:
2919 case ARM::VLD4q32Pseudo_UPD:
2920 case ARM::VLD4q8oddPseudo:
2921 case ARM::VLD4q16oddPseudo:
2922 case ARM::VLD4q32oddPseudo:
2923 case ARM::VLD4q8oddPseudo_UPD:
2924 case ARM::VLD4q16oddPseudo_UPD:
2925 case ARM::VLD4q32oddPseudo_UPD:
2926 case ARM::VLD3DUPd8Pseudo:
2927 case ARM::VLD3DUPd16Pseudo:
2928 case ARM::VLD3DUPd32Pseudo:
2929 case ARM::VLD3DUPd8Pseudo_UPD:
2930 case ARM::VLD3DUPd16Pseudo_UPD:
2931 case ARM::VLD3DUPd32Pseudo_UPD:
2932 case ARM::VLD4DUPd8Pseudo:
2933 case ARM::VLD4DUPd16Pseudo:
2934 case ARM::VLD4DUPd32Pseudo:
2935 case ARM::VLD4DUPd8Pseudo_UPD:
2936 case ARM::VLD4DUPd16Pseudo_UPD:
2937 case ARM::VLD4DUPd32Pseudo_UPD:
2938 case ARM::VLD2DUPq8EvenPseudo:
2939 case ARM::VLD2DUPq8OddPseudo:
2940 case ARM::VLD2DUPq16EvenPseudo:
2941 case ARM::VLD2DUPq16OddPseudo:
2942 case ARM::VLD2DUPq32EvenPseudo:
2943 case ARM::VLD2DUPq32OddPseudo:
2944 case ARM::VLD2DUPq8OddPseudoWB_fixed:
2945 case ARM::VLD2DUPq8OddPseudoWB_register:
2946 case ARM::VLD2DUPq16OddPseudoWB_fixed:
2947 case ARM::VLD2DUPq16OddPseudoWB_register:
2948 case ARM::VLD2DUPq32OddPseudoWB_fixed:
2949 case ARM::VLD2DUPq32OddPseudoWB_register:
2950 case ARM::VLD3DUPq8EvenPseudo:
2951 case ARM::VLD3DUPq8OddPseudo:
2952 case ARM::VLD3DUPq16EvenPseudo:
2953 case ARM::VLD3DUPq16OddPseudo:
2954 case ARM::VLD3DUPq32EvenPseudo:
2955 case ARM::VLD3DUPq32OddPseudo:
2956 case ARM::VLD3DUPq8OddPseudo_UPD:
2957 case ARM::VLD3DUPq16OddPseudo_UPD:
2958 case ARM::VLD3DUPq32OddPseudo_UPD:
2959 case ARM::VLD4DUPq8EvenPseudo:
2960 case ARM::VLD4DUPq8OddPseudo:
2961 case ARM::VLD4DUPq16EvenPseudo:
2962 case ARM::VLD4DUPq16OddPseudo:
2963 case ARM::VLD4DUPq32EvenPseudo:
2964 case ARM::VLD4DUPq32OddPseudo:
2965 case ARM::VLD4DUPq8OddPseudo_UPD:
2966 case ARM::VLD4DUPq16OddPseudo_UPD:
2967 case ARM::VLD4DUPq32OddPseudo_UPD:
2971 case ARM::VST2q8Pseudo:
2972 case ARM::VST2q16Pseudo:
2973 case ARM::VST2q32Pseudo:
2974 case ARM::VST2q8PseudoWB_fixed:
2975 case ARM::VST2q16PseudoWB_fixed:
2976 case ARM::VST2q32PseudoWB_fixed:
2977 case ARM::VST2q8PseudoWB_register:
2978 case ARM::VST2q16PseudoWB_register:
2979 case ARM::VST2q32PseudoWB_register:
2980 case ARM::VST3d8Pseudo:
2981 case ARM::VST3d16Pseudo:
2982 case ARM::VST3d32Pseudo:
2983 case ARM::VST1d8TPseudo:
2984 case ARM::VST1d8TPseudoWB_fixed:
2985 case ARM::VST1d8TPseudoWB_register:
2986 case ARM::VST1d16TPseudo:
2987 case ARM::VST1d16TPseudoWB_fixed:
2988 case ARM::VST1d16TPseudoWB_register:
2989 case ARM::VST1d32TPseudo:
2990 case ARM::VST1d32TPseudoWB_fixed:
2991 case ARM::VST1d32TPseudoWB_register:
2992 case ARM::VST1d64TPseudo:
2993 case ARM::VST1d64TPseudoWB_fixed:
2994 case ARM::VST1d64TPseudoWB_register:
2995 case ARM::VST3d8Pseudo_UPD:
2996 case ARM::VST3d16Pseudo_UPD:
2997 case ARM::VST3d32Pseudo_UPD:
2998 case ARM::VST3q8Pseudo_UPD:
2999 case ARM::VST3q16Pseudo_UPD:
3000 case ARM::VST3q32Pseudo_UPD:
3001 case ARM::VST3q8oddPseudo:
3002 case ARM::VST3q16oddPseudo:
3003 case ARM::VST3q32oddPseudo:
3004 case ARM::VST3q8oddPseudo_UPD:
3005 case ARM::VST3q16oddPseudo_UPD:
3006 case ARM::VST3q32oddPseudo_UPD:
3007 case ARM::VST4d8Pseudo:
3008 case ARM::VST4d16Pseudo:
3009 case ARM::VST4d32Pseudo:
3010 case ARM::VST1d8QPseudo:
3011 case ARM::VST1d8QPseudoWB_fixed:
3012 case ARM::VST1d8QPseudoWB_register:
3013 case ARM::VST1d16QPseudo:
3014 case ARM::VST1d16QPseudoWB_fixed:
3015 case ARM::VST1d16QPseudoWB_register:
3016 case ARM::VST1d32QPseudo:
3017 case ARM::VST1d32QPseudoWB_fixed:
3018 case ARM::VST1d32QPseudoWB_register:
3019 case ARM::VST1d64QPseudo:
3020 case ARM::VST1d64QPseudoWB_fixed:
3021 case ARM::VST1d64QPseudoWB_register:
3022 case ARM::VST4d8Pseudo_UPD:
3023 case ARM::VST4d16Pseudo_UPD:
3024 case ARM::VST4d32Pseudo_UPD:
3025 case ARM::VST1q8HighQPseudo:
3026 case ARM::VST1q8LowQPseudo_UPD:
3027 case ARM::VST1q8HighTPseudo:
3028 case ARM::VST1q8LowTPseudo_UPD:
3029 case ARM::VST1q16HighQPseudo:
3030 case ARM::VST1q16LowQPseudo_UPD:
3031 case ARM::VST1q16HighTPseudo:
3032 case ARM::VST1q16LowTPseudo_UPD:
3033 case ARM::VST1q32HighQPseudo:
3034 case ARM::VST1q32LowQPseudo_UPD:
3035 case ARM::VST1q32HighTPseudo:
3036 case ARM::VST1q32LowTPseudo_UPD:
3037 case ARM::VST1q64HighQPseudo:
3038 case ARM::VST1q64LowQPseudo_UPD:
3039 case ARM::VST1q64HighTPseudo:
3040 case ARM::VST1q64LowTPseudo_UPD:
3041 case ARM::VST1q8HighTPseudo_UPD:
3042 case ARM::VST1q16HighTPseudo_UPD:
3043 case ARM::VST1q32HighTPseudo_UPD:
3044 case ARM::VST1q64HighTPseudo_UPD:
3045 case ARM::VST1q8HighQPseudo_UPD:
3046 case ARM::VST1q16HighQPseudo_UPD:
3047 case ARM::VST1q32HighQPseudo_UPD:
3048 case ARM::VST1q64HighQPseudo_UPD:
3049 case ARM::VST4q8Pseudo_UPD:
3050 case ARM::VST4q16Pseudo_UPD:
3051 case ARM::VST4q32Pseudo_UPD:
3052 case ARM::VST4q8oddPseudo:
3053 case ARM::VST4q16oddPseudo:
3054 case ARM::VST4q32oddPseudo:
3055 case ARM::VST4q8oddPseudo_UPD:
3056 case ARM::VST4q16oddPseudo_UPD:
3057 case ARM::VST4q32oddPseudo_UPD:
3061 case ARM::VLD1LNq8Pseudo:
3062 case ARM::VLD1LNq16Pseudo:
3063 case ARM::VLD1LNq32Pseudo:
3064 case ARM::VLD1LNq8Pseudo_UPD:
3065 case ARM::VLD1LNq16Pseudo_UPD:
3066 case ARM::VLD1LNq32Pseudo_UPD:
3067 case ARM::VLD2LNd8Pseudo:
3068 case ARM::VLD2LNd16Pseudo:
3069 case ARM::VLD2LNd32Pseudo:
3070 case ARM::VLD2LNq16Pseudo:
3071 case ARM::VLD2LNq32Pseudo:
3072 case ARM::VLD2LNd8Pseudo_UPD:
3073 case ARM::VLD2LNd16Pseudo_UPD:
3074 case ARM::VLD2LNd32Pseudo_UPD:
3075 case ARM::VLD2LNq16Pseudo_UPD:
3076 case ARM::VLD2LNq32Pseudo_UPD:
3077 case ARM::VLD3LNd8Pseudo:
3078 case ARM::VLD3LNd16Pseudo:
3079 case ARM::VLD3LNd32Pseudo:
3080 case ARM::VLD3LNq16Pseudo:
3081 case ARM::VLD3LNq32Pseudo:
3082 case ARM::VLD3LNd8Pseudo_UPD:
3083 case ARM::VLD3LNd16Pseudo_UPD:
3084 case ARM::VLD3LNd32Pseudo_UPD:
3085 case ARM::VLD3LNq16Pseudo_UPD:
3086 case ARM::VLD3LNq32Pseudo_UPD:
3087 case ARM::VLD4LNd8Pseudo:
3088 case ARM::VLD4LNd16Pseudo:
3089 case ARM::VLD4LNd32Pseudo:
3090 case ARM::VLD4LNq16Pseudo:
3091 case ARM::VLD4LNq32Pseudo:
3092 case ARM::VLD4LNd8Pseudo_UPD:
3093 case ARM::VLD4LNd16Pseudo_UPD:
3094 case ARM::VLD4LNd32Pseudo_UPD:
3095 case ARM::VLD4LNq16Pseudo_UPD:
3096 case ARM::VLD4LNq32Pseudo_UPD:
3097 case ARM::VST1LNq8Pseudo:
3098 case ARM::VST1LNq16Pseudo:
3099 case ARM::VST1LNq32Pseudo:
3100 case ARM::VST1LNq8Pseudo_UPD:
3101 case ARM::VST1LNq16Pseudo_UPD:
3102 case ARM::VST1LNq32Pseudo_UPD:
3103 case ARM::VST2LNd8Pseudo:
3104 case ARM::VST2LNd16Pseudo:
3105 case ARM::VST2LNd32Pseudo:
3106 case ARM::VST2LNq16Pseudo:
3107 case ARM::VST2LNq32Pseudo:
3108 case ARM::VST2LNd8Pseudo_UPD:
3109 case ARM::VST2LNd16Pseudo_UPD:
3110 case ARM::VST2LNd32Pseudo_UPD:
3111 case ARM::VST2LNq16Pseudo_UPD:
3112 case ARM::VST2LNq32Pseudo_UPD:
3113 case ARM::VST3LNd8Pseudo:
3114 case ARM::VST3LNd16Pseudo:
3115 case ARM::VST3LNd32Pseudo:
3116 case ARM::VST3LNq16Pseudo:
3117 case ARM::VST3LNq32Pseudo:
3118 case ARM::VST3LNd8Pseudo_UPD:
3119 case ARM::VST3LNd16Pseudo_UPD:
3120 case ARM::VST3LNd32Pseudo_UPD:
3121 case ARM::VST3LNq16Pseudo_UPD:
3122 case ARM::VST3LNq32Pseudo_UPD:
3123 case ARM::VST4LNd8Pseudo:
3124 case ARM::VST4LNd16Pseudo:
3125 case ARM::VST4LNd32Pseudo:
3126 case ARM::VST4LNq16Pseudo:
3127 case ARM::VST4LNq32Pseudo:
3128 case ARM::VST4LNd8Pseudo_UPD:
3129 case ARM::VST4LNd16Pseudo_UPD:
3130 case ARM::VST4LNd32Pseudo_UPD:
3131 case ARM::VST4LNq16Pseudo_UPD:
3132 case ARM::VST4LNq32Pseudo_UPD:
3136 case ARM::VTBL3Pseudo: ExpandVTBL(MBBI, ARM::VTBL3, false); return true;
3137 case ARM::VTBL4Pseudo: ExpandVTBL(MBBI, ARM::VTBL4, false); return true;
3138 case ARM::VTBX3Pseudo: ExpandVTBL(MBBI, ARM::VTBX3, true); return true;
3139 case ARM::VTBX4Pseudo: ExpandVTBL(MBBI, ARM::VTBX4, true); return true;
3141 case ARM::MQQPRLoad:
3142 case ARM::MQQPRStore:
3143 case ARM::MQQQQPRLoad:
3144 case ARM::MQQQQPRStore:
3148 case ARM::tCMP_SWAP_8:
3150 return ExpandCMP_SWAP(MBB, MBBI, ARM::t2LDREXB, ARM::t2STREXB, ARM::tUXTB,
3152 case ARM::tCMP_SWAP_16:
3154 return ExpandCMP_SWAP(MBB, MBBI, ARM::t2LDREXH, ARM::t2STREXH, ARM::tUXTH,
3156 case ARM::tCMP_SWAP_32:
3158 return ExpandCMP_SWAP(MBB, MBBI, ARM::t2LDREX, ARM::t2STREX, 0, NextMBBI);
3160 case ARM::CMP_SWAP_8:
3162 return ExpandCMP_SWAP(MBB, MBBI, ARM::LDREXB, ARM::STREXB, ARM::UXTB,
3164 case ARM::CMP_SWAP_16:
3166 return ExpandCMP_SWAP(MBB, MBBI, ARM::LDREXH, ARM::STREXH, ARM::UXTH,
3168 case ARM::CMP_SWAP_32:
3170 return ExpandCMP_SWAP(MBB, MBBI, ARM::LDREX, ARM::STREX, 0, NextMBBI);
3172 case ARM::CMP_SWAP_64:
3175 case ARM::tBL_PUSHLR:
3176 case ARM::BL_PUSHLR: {
3177 const bool Thumb = Opcode == ARM::tBL_PUSHLR;
3179 assert(Reg == ARM::LR && "expect LR register!");
3183 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::tPUSH))
3188 MIB = BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::tBL));
3191 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::STMDB_UPD))
3192 .addReg(ARM::SP, RegState::Define)
3193 .addReg(ARM::SP)
3198 MIB = BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::BL));
3206 case ARM::t2CALL_BTI: {
3209 BuildMI(MF, MI.getDebugLoc(), TII->get(ARM::tBL));
3217 Bundler.append(BuildMI(MF, MI.getDebugLoc(), TII->get(ARM::t2BTI)));
3222 case ARM::LOADDUAL:
3223 case ARM::STOREDUAL: {
3228 TII->get(Opcode == ARM::LOADDUAL ? ARM::LDRD : ARM::STRD))
3229 .addReg(TRI->getSubReg(PairReg, ARM::gsub_0),
3230 Opcode == ARM::LOADDUAL ? RegState::Define : 0)
3231 .addReg(TRI->getSubReg(PairReg, ARM::gsub_1),
3232 Opcode == ARM::LOADDUAL ? RegState::Define : 0);
3262 LLVM_DEBUG(dbgs() << "********** ARM EXPAND PSEUDO INSTRUCTIONS **********\n"
3269 MF.verify(this, "After expanding ARM pseudo instructions.");