Lines Matching refs:iterator
223 void reportUnsupported(const MachineBasicBlock::iterator &MI,
239 constructFromMIWithMMO(const MachineBasicBlock::iterator &MI) const;
248 getLoadInfo(const MachineBasicBlock::iterator &MI) const;
253 getStoreInfo(const MachineBasicBlock::iterator &MI) const;
258 getAtomicFenceInfo(const MachineBasicBlock::iterator &MI) const;
263 getAtomicCmpxchgOrRmwInfo(const MachineBasicBlock::iterator &MI) const;
284 bool enableNamedBit(const MachineBasicBlock::iterator MI,
295 virtual bool enableLoadCacheBypass(const MachineBasicBlock::iterator &MI,
302 virtual bool enableStoreCacheBypass(const MachineBasicBlock::iterator &MI,
309 virtual bool enableRMWCacheBypass(const MachineBasicBlock::iterator &MI,
316 virtual bool enableVolatileAndOrNonTemporal(MachineBasicBlock::iterator &MI,
322 virtual bool expandSystemScopeStore(MachineBasicBlock::iterator &MI) const {
333 virtual bool insertWait(MachineBasicBlock::iterator &MI,
345 virtual bool insertAcquire(MachineBasicBlock::iterator &MI,
356 virtual bool insertRelease(MachineBasicBlock::iterator &MI,
366 MachineBasicBlock::iterator &MI) const {
376 bool enableGLCBit(const MachineBasicBlock::iterator &MI) const {
382 bool enableSLCBit(const MachineBasicBlock::iterator &MI) const {
390 bool enableLoadCacheBypass(const MachineBasicBlock::iterator &MI,
394 bool enableStoreCacheBypass(const MachineBasicBlock::iterator &MI,
398 bool enableRMWCacheBypass(const MachineBasicBlock::iterator &MI,
402 bool enableVolatileAndOrNonTemporal(MachineBasicBlock::iterator &MI,
407 bool insertWait(MachineBasicBlock::iterator &MI,
414 bool insertAcquire(MachineBasicBlock::iterator &MI,
419 bool insertRelease(MachineBasicBlock::iterator &MI,
431 bool insertAcquire(MachineBasicBlock::iterator &MI,
443 bool enableLoadCacheBypass(const MachineBasicBlock::iterator &MI,
447 bool enableStoreCacheBypass(const MachineBasicBlock::iterator &MI,
451 bool enableRMWCacheBypass(const MachineBasicBlock::iterator &MI,
455 bool enableVolatileAndOrNonTemporal(MachineBasicBlock::iterator &MI,
460 bool insertWait(MachineBasicBlock::iterator &MI,
467 bool insertAcquire(MachineBasicBlock::iterator &MI,
472 bool insertRelease(MachineBasicBlock::iterator &MI,
484 bool enableSC0Bit(const MachineBasicBlock::iterator &MI) const {
490 bool enableSC1Bit(const MachineBasicBlock::iterator &MI) const {
496 bool enableNTBit(const MachineBasicBlock::iterator &MI) const {
504 bool enableLoadCacheBypass(const MachineBasicBlock::iterator &MI,
508 bool enableStoreCacheBypass(const MachineBasicBlock::iterator &MI,
512 bool enableRMWCacheBypass(const MachineBasicBlock::iterator &MI,
516 bool enableVolatileAndOrNonTemporal(MachineBasicBlock::iterator &MI,
521 bool insertAcquire(MachineBasicBlock::iterator &MI, SIAtomicScope Scope,
524 bool insertRelease(MachineBasicBlock::iterator &MI, SIAtomicScope Scope,
529 MachineBasicBlock::iterator &MI) const override {
548 bool enableDLCBit(const MachineBasicBlock::iterator &MI) const {
556 bool enableLoadCacheBypass(const MachineBasicBlock::iterator &MI,
560 bool enableVolatileAndOrNonTemporal(MachineBasicBlock::iterator &MI,
565 bool insertWait(MachineBasicBlock::iterator &MI,
572 bool insertAcquire(MachineBasicBlock::iterator &MI,
582 bool enableLoadCacheBypass(const MachineBasicBlock::iterator &MI,
586 bool enableVolatileAndOrNonTemporal(MachineBasicBlock::iterator &MI,
596 bool setTH(const MachineBasicBlock::iterator MI,
600 bool setScope(const MachineBasicBlock::iterator MI,
610 insertWaitsBeforeSystemScopeStore(const MachineBasicBlock::iterator MI) const;
612 bool setAtomicScope(const MachineBasicBlock::iterator &MI,
618 bool insertWait(MachineBasicBlock::iterator &MI, SIAtomicScope Scope,
622 bool insertAcquire(MachineBasicBlock::iterator &MI, SIAtomicScope Scope,
625 bool enableVolatileAndOrNonTemporal(MachineBasicBlock::iterator &MI,
630 bool expandSystemScopeStore(MachineBasicBlock::iterator &MI) const override;
632 bool insertRelease(MachineBasicBlock::iterator &MI, SIAtomicScope Scope,
636 bool enableLoadCacheBypass(const MachineBasicBlock::iterator &MI,
642 bool enableStoreCacheBypass(const MachineBasicBlock::iterator &MI,
648 bool enableRMWCacheBypass(const MachineBasicBlock::iterator &MI,
662 std::list<MachineBasicBlock::iterator> AtomicPseudoMIs;
677 MachineBasicBlock::iterator &MI);
681 MachineBasicBlock::iterator &MI);
685 MachineBasicBlock::iterator &MI);
689 MachineBasicBlock::iterator &MI);
753 void SIMemOpAccess::reportUnsupported(const MachineBasicBlock::iterator &MI,
813 const MachineBasicBlock::iterator &MI) const {
875 SIMemOpAccess::getLoadInfo(const MachineBasicBlock::iterator &MI) const {
889 SIMemOpAccess::getStoreInfo(const MachineBasicBlock::iterator &MI) const {
903 SIMemOpAccess::getAtomicFenceInfo(const MachineBasicBlock::iterator &MI) const {
936 const MachineBasicBlock::iterator &MI) const {
955 bool SICacheControl::enableNamedBit(const MachineBasicBlock::iterator MI,
984 const MachineBasicBlock::iterator &MI,
1019 const MachineBasicBlock::iterator &MI,
1032 const MachineBasicBlock::iterator &MI,
1047 MachineBasicBlock::iterator &MI, SIAtomicAddrSpace AddrSpace, SIMemOp Op,
1091 bool SIGfx6CacheControl::insertWait(MachineBasicBlock::iterator &MI,
1189 bool SIGfx6CacheControl::insertAcquire(MachineBasicBlock::iterator &MI,
1234 bool SIGfx6CacheControl::insertRelease(MachineBasicBlock::iterator &MI,
1243 bool SIGfx7CacheControl::insertAcquire(MachineBasicBlock::iterator &MI,
1295 const MachineBasicBlock::iterator &MI,
1337 const MachineBasicBlock::iterator &MI,
1372 const MachineBasicBlock::iterator &MI,
1400 MachineBasicBlock::iterator &MI, SIAtomicAddrSpace AddrSpace, SIMemOp Op,
1444 bool SIGfx90ACacheControl::insertWait(MachineBasicBlock::iterator &MI,
1472 bool SIGfx90ACacheControl::insertAcquire(MachineBasicBlock::iterator &MI,
1538 bool SIGfx90ACacheControl::insertRelease(MachineBasicBlock::iterator &MI,
1589 const MachineBasicBlock::iterator &MI, SIAtomicScope Scope,
1633 const MachineBasicBlock::iterator &MI,
1673 const MachineBasicBlock::iterator &MI, SIAtomicScope Scope,
1702 MachineBasicBlock::iterator &MI, SIAtomicAddrSpace AddrSpace, SIMemOp Op,
1741 bool SIGfx940CacheControl::insertAcquire(MachineBasicBlock::iterator &MI,
1827 bool SIGfx940CacheControl::insertRelease(MachineBasicBlock::iterator &MI,
1891 const MachineBasicBlock::iterator &MI,
1934 MachineBasicBlock::iterator &MI, SIAtomicAddrSpace AddrSpace, SIMemOp Op,
1984 bool SIGfx10CacheControl::insertWait(MachineBasicBlock::iterator &MI,
2105 bool SIGfx10CacheControl::insertAcquire(MachineBasicBlock::iterator &MI,
2164 const MachineBasicBlock::iterator &MI, SIAtomicScope Scope,
2205 MachineBasicBlock::iterator &MI, SIAtomicAddrSpace AddrSpace, SIMemOp Op,
2258 bool SIGfx12CacheControl::setTH(const MachineBasicBlock::iterator MI,
2273 bool SIGfx12CacheControl::setScope(const MachineBasicBlock::iterator MI,
2289 const MachineBasicBlock::iterator MI) const {
2304 bool SIGfx12CacheControl::insertWait(MachineBasicBlock::iterator &MI,
2400 bool SIGfx12CacheControl::insertAcquire(MachineBasicBlock::iterator &MI,
2456 bool SIGfx12CacheControl::insertRelease(MachineBasicBlock::iterator &MI,
2523 MachineBasicBlock::iterator &MI, SIAtomicAddrSpace AddrSpace, SIMemOp Op,
2564 MachineBasicBlock::iterator &MI) const {
2572 bool SIGfx12CacheControl::setAtomicScope(const MachineBasicBlock::iterator &MI,
2622 MachineBasicBlock::iterator &MI) {
2668 MachineBasicBlock::iterator &MI) {
2705 MachineBasicBlock::iterator &MI) {
2755 MachineBasicBlock::iterator &MI) {