Lines Matching defs:auto

276   auto tryFoldToInline = [&](uint32_t Imm) -> bool {
378     auto Liveness = MBB->computeRegisterLiveness(TRI, AMDGPU::VCC, MI, 16);
451   return any_of(FoldList, [&](const auto &C) { return C.UseMI == MI; });
472   auto tryToFoldAsFMAAKorMK = [&]() {
636         auto &Op = MI->getOperand(i);
738     auto SubImm = Op->getImm();
780     for (auto &Use : MRI->use_nodbg_operands(RegSeqDstReg))
782     for (auto *RSUse : UsesToProcess) {
877       const auto &SrcOp = UseMI->getOperand(UseOpIdx);
928             auto Tmp = MRI->createVirtualRegister(&AMDGPU::AGPR_32RegClass);
933             auto Src = getRegSubRegPair(*Def);
947             auto Src = getRegSubRegPair(*Def);
955               auto Tmp = MRI->createVirtualRegister(&AMDGPU::AGPR_32RegClass);
970             auto Tmp = MRI->createVirtualRegister(&AMDGPU::AGPR_32RegClass);
1319     auto *Src0Imm = getImmOrMaterializedImm(*Src0);
1320     auto *Src1Imm = getImmOrMaterializedImm(*Src1);
1334   auto &NewDesc =
1382     for (auto &UseMI :
1400   for (auto &Use : MRI->use_nodbg_operands(Dst.getReg()))
1402   for (auto *U : UsesToProcess) {
1489   auto *InstToErase = &MI;
1491     auto &SrcOp = InstToErase->getOperand(1);
1492     auto SrcReg = SrcOp.isReg() ? SrcOp.getReg() : Register();
1776   auto Reg = MI.getOperand(0).getReg();
1786   for (auto &[Op, SubIdx] : Defs) {
1819   const auto *NewDstRC = TRI->getEquivalentAGPRClass(MRI->getRegClass(Reg));
1820   auto Dst = MRI->createVirtualRegister(NewDstRC);
1821   auto RS = BuildMI(*MI.getParent(), MI, MI.getDebugLoc(),
1824   for (auto &[Def, SubIdx] : Defs) {
1943     if (const auto *SubRC = TRI->getSubRegisterClass(CopyInRC, AGPRRegMask))
2122   for (auto &MI : MBB) {
2140   for (const auto &[Entry, MOs] : RegToMO) {
2144     const auto [Reg, SubReg] = Entry;
2197     for (auto &MI : make_early_inc_range(*MBB)) {