Lines Matching defs:const
33 R600InstrInfo::R600InstrInfo(const R600Subtarget &ST)
36 bool R600InstrInfo::isVector(const MachineInstr &MI) const {
42 const DebugLoc &DL, MCRegister DestReg,
43 MCRegister SrcReg, bool KillSrc) const {
76 MachineBasicBlock::iterator MBBI) const {
86 bool R600InstrInfo::isMov(unsigned Opcode) const {
97 bool R600InstrInfo::isReductionOp(unsigned Opcode) const {
101 bool R600InstrInfo::isCubeOp(unsigned Opcode) const {
112 bool R600InstrInfo::isALUInstr(unsigned Opcode) const {
118 bool R600InstrInfo::hasInstrModifiers(unsigned Opcode) const {
126 bool R600InstrInfo::isLDSInstr(unsigned Opcode) const {
134 bool R600InstrInfo::isLDSRetInstr(unsigned Opcode) const {
138 bool R600InstrInfo::canBeConsideredALU(const MachineInstr &MI) const {
156 bool R600InstrInfo::isTransOnly(unsigned Opcode) const {
162 bool R600InstrInfo::isTransOnly(const MachineInstr &MI) const {
166 bool R600InstrInfo::isVectorOnly(unsigned Opcode) const {
170 bool R600InstrInfo::isVectorOnly(const MachineInstr &MI) const {
174 bool R600InstrInfo::isExport(unsigned Opcode) const {
178 bool R600InstrInfo::usesVertexCache(unsigned Opcode) const {
182 bool R600InstrInfo::usesVertexCache(const MachineInstr &MI) const {
183 const MachineFunction *MF = MI.getParent()->getParent();
188 bool R600InstrInfo::usesTextureCache(unsigned Opcode) const {
192 bool R600InstrInfo::usesTextureCache(const MachineInstr &MI) const {
193 const MachineFunction *MF = MI.getParent()->getParent();
199 bool R600InstrInfo::mustBeLastInClause(unsigned Opcode) const {
209 bool R600InstrInfo::usesAddressRegister(MachineInstr &MI) const {
213 bool R600InstrInfo::definesAddressRegister(MachineInstr &MI) const {
217 bool R600InstrInfo::readsLDSSrcReg(const MachineInstr &MI) const {
233 int R600InstrInfo::getSelIdx(unsigned Opcode, unsigned SrcIdx) const {
234 static const unsigned SrcSelTable[][2] = {
248 for (const auto &Row : SrcSelTable) {
257 R600InstrInfo::getSrcs(MachineInstr &MI) const {
261 static const unsigned OpTable[8][2] = {
272 for (const auto &Op : OpTable) {
285 static const unsigned OpTable[3][2] = {
291 for (const auto &Op : OpTable) {
318 const DenseMap<unsigned, unsigned> &PV,
319 unsigned &ConstCount) const {
321 const std::pair<int, unsigned> DummyPair(-1, 0);
324 for (const auto &Src : getSrcs(MI)) {
406 const std::vector<std::vector<std::pair<int, unsigned>>> &IGSrcs,
407 const std::vector<R600InstrInfo::BankSwizzle> &Swz,
408 const std::vector<std::pair<int, unsigned>> &TransSrcs,
409 R600InstrInfo::BankSwizzle TransSwz) const {
413 const std::vector<std::pair<int, unsigned>> &Srcs =
416 const std::pair<int, unsigned> &Src = Srcs[j];
437 const std::pair<int, unsigned> &Src = TransSrcs[i];
475 const std::vector<std::vector<std::pair<int, unsigned>>> &IGSrcs,
477 const std::vector<std::pair<int, unsigned>> &TransSrcs,
478 R600InstrInfo::BankSwizzle TransSwz) const {
489 /// a const, and can't read a gpr at cycle 1 if they read 2 const.
492 const std::vector<std::pair<int, unsigned>> &TransOps,
498 const std::pair<int, unsigned> &Src = TransOps[i];
511 R600InstrInfo::fitsReadPortLimitations(const std::vector<MachineInstr *> &IG,
512 const DenseMap<unsigned, unsigned> &PV,
515 const {
536 static const R600InstrInfo::BankSwizzle TransSwz[] = {
557 R600InstrInfo::fitsConstReadLimitations(const std::vector<unsigned> &Consts)
558 const {
582 R600InstrInfo::fitsConstReadLimitations(const std::vector<MachineInstr *> &MIs)
583 const {
590 for (const auto &Src : getSrcs(*MI)) {
609 R600InstrInfo::CreateTargetScheduleState(const TargetSubtargetInfo &STI) const {
610 const InstrItineraryData *II = STI.getInstrItineraryData();
611 return static_cast<const R600Subtarget &>(STI).createDFAPacketizer(II);
651 bool AllowModify) const {
734 const DebugLoc &DL,
735 int *BytesAdded) const {
776 int *BytesRemoved) const {
834 bool R600InstrInfo::isPredicated(const MachineInstr &MI) const {
849 bool R600InstrInfo::isPredicable(const MachineInstr &MI) const {
874 BranchProbability Probability) const{
885 BranchProbability Probability) const {
893 const {
899 MachineBasicBlock &FMBB) const {
904 R600InstrInfo::reverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const {
939 bool SkipDead) const {
944 ArrayRef<MachineOperand> Pred) const {
977 unsigned int R600InstrInfo::getPredicationCost(const MachineInstr &) const {
981 unsigned int R600InstrInfo::getInstrLatency(const InstrItineraryData *ItinData,
982 const MachineInstr &,
983 unsigned *PredCost) const {
990 unsigned Channel) const {
995 bool R600InstrInfo::expandPostRAPseudo(MachineInstr &MI) const {
1062 const MachineFunction &MF,
1063 const R600RegisterInfo &TRI) const {
1064 const R600Subtarget &ST = MF.getSubtarget<R600Subtarget>();
1065 const R600FrameLowering *TFL = ST.getFrameLowering();
1081 const TargetRegisterClass *R600InstrInfo::getIndirectAddrRegClass() const {
1088 unsigned OffsetReg) const {
1096 unsigned AddrChan) const {
1120 unsigned OffsetReg) const {
1128 unsigned AddrChan) const {
1151 int R600InstrInfo::getIndirectIndexBegin(const MachineFunction &MF) const {
1152 const MachineRegisterInfo &MRI = MF.getRegInfo();
1153 const MachineFrameInfo &MFI = MF.getFrameInfo();
1164 const TargetRegisterClass *IndirectRC = getIndirectAddrRegClass();
1183 int R600InstrInfo::getIndirectIndexEnd(const MachineFunction &MF) const {
1185 const MachineFrameInfo &MFI = MF.getFrameInfo();
1196 const R600Subtarget &ST = MF.getSubtarget<R600Subtarget>();
1197 const R600FrameLowering *TFL = ST.getFrameLowering();
1205 unsigned R600InstrInfo::getMaxAlusPerClause() const {
1214 unsigned Src1Reg) const {
1252 static const unsigned Ops[] = \
1290 const {
1304 static const unsigned Operands[14] = {
1339 uint64_t Imm) const {
1348 unsigned DstReg, unsigned SrcReg) const {
1352 int R600InstrInfo::getOperandIdx(const MachineInstr &MI, unsigned Op) const {
1356 int R600InstrInfo::getOperandIdx(unsigned Opcode, unsigned Op) const {
1361 int64_t Imm) const {
1373 unsigned Flag) const {
1438 unsigned Flag) const {
1459 unsigned Flag) const {