Lines Matching defs:const

42 AArch64RegisterInfo::AArch64RegisterInfo(const Triple &TT)
53                                       unsigned &RegToUseForCFI) const {
70 const MCPhysReg *
71 AArch64RegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
148 const MCPhysReg *
149 AArch64RegisterInfo::getDarwinCalleeSavedRegs(const MachineFunction *MF) const {
203 const MCPhysReg *AArch64RegisterInfo::getCalleeSavedRegsViaCopy(
204     const MachineFunction *MF) const {
213     MachineFunction &MF) const {
214   const MCPhysReg *CSRs = getCalleeSavedRegs(&MF);
216   for (const MCPhysReg *I = CSRs; *I; ++I)
229 const TargetRegisterClass *
230 AArch64RegisterInfo::getSubClassWithSubReg(const TargetRegisterClass *RC,
231                                        unsigned Idx) const {
242 const uint32_t *
243 AArch64RegisterInfo::getDarwinCallPreservedMask(const MachineFunction &MF,
244                                                 CallingConv::ID CC) const {
278 const uint32_t *
279 AArch64RegisterInfo::getCallPreservedMask(const MachineFunction &MF,
280                                           CallingConv::ID CC) const {
331 const uint32_t *AArch64RegisterInfo::getCustomEHPadPreservedMask(
332     const MachineFunction &MF) const {
339 const uint32_t *AArch64RegisterInfo::getTLSCallPreservedMask() const {
348                                                  const uint32_t **Mask) const {
366 const uint32_t *AArch64RegisterInfo::getSMStartStopCallPreservedMask() const {
370 const uint32_t *
371 AArch64RegisterInfo::SMEABISupportRoutinesCallPreservedMaskFromX0() const {
375 const uint32_t *AArch64RegisterInfo::getNoPreservedMask() const {
379 const uint32_t *
380 AArch64RegisterInfo::getThisReturnPreservedMask(const MachineFunction &MF,
381                                                 CallingConv::ID CC) const {
395 const uint32_t *AArch64RegisterInfo::getWindowsStackProbePreservedMask() const {
400 AArch64RegisterInfo::explainReservedReg(const MachineFunction &MF,
401                                         MCRegister PhysReg) const {
427 AArch64RegisterInfo::getStrictlyReservedRegs(const MachineFunction &MF) const {
428   const AArch64FrameLowering *TFI = getFrameLowering(MF);
496 AArch64RegisterInfo::getReservedRegs(const MachineFunction &MF) const {
519 bool AArch64RegisterInfo::isReservedReg(const MachineFunction &MF,
520                                         MCRegister Reg) const {
524 bool AArch64RegisterInfo::isStrictlyReservedReg(const MachineFunction &MF,
525                                                 MCRegister Reg) const {
529 bool AArch64RegisterInfo::isAnyArgRegReserved(const MachineFunction &MF) const {
536     const MachineFunction &MF) const {
537   const Function &F = MF.getFunction();
542 bool AArch64RegisterInfo::isAsmClobberable(const MachineFunction &MF,
543                                           MCRegister PhysReg) const {
558 const TargetRegisterClass *
559 AArch64RegisterInfo::getPointerRegClass(const MachineFunction &MF,
560                                       unsigned Kind) const {
564 const TargetRegisterClass *
565 AArch64RegisterInfo::getCrossCopyRegClass(const TargetRegisterClass *RC) const {
571 unsigned AArch64RegisterInfo::getBaseRegister() const { return AArch64::X19; }
573 bool AArch64RegisterInfo::hasBasePointer(const MachineFunction &MF) const {
574   const MachineFrameInfo &MFI = MF.getFrameInfo();
590       const AArch64FunctionInfo *AFI = MF.getInfo<AArch64FunctionInfo>();
610 bool AArch64RegisterInfo::isArgumentRegister(const MachineFunction &MF,
611                                              MCRegister Reg) const {
613   const AArch64Subtarget &STI = MF.getSubtarget<AArch64Subtarget>();
691 AArch64RegisterInfo::getFrameRegister(const MachineFunction &MF) const {
692   const AArch64FrameLowering *TFI = getFrameLowering(MF);
697     const MachineFunction &MF) const {
702     const MachineFunction &MF) const {
707 AArch64RegisterInfo::useFPForScavengingIndex(const MachineFunction &MF) const {
716   const AArch64FrameLowering &TFI = *getFrameLowering(MF);
717   const AArch64FunctionInfo *AFI = MF.getInfo<AArch64FunctionInfo>();
725     const MachineFunction &MF) const {
730 AArch64RegisterInfo::cannotEliminateFrame(const MachineFunction &MF) const {
731   const MachineFrameInfo &MFI = MF.getFrameInfo();
742                                             int64_t Offset) const {
765   const AArch64FrameLowering *TFI = getFrameLowering(MF);
805 bool AArch64RegisterInfo::isFrameOffsetLegal(const MachineInstr *MI,
807                                              int64_t Offset) const {
818                                                   int64_t Offset) const {
823   const MachineFunction &MF = *MBB->getParent();
824   const AArch64InstrInfo *TII =
826   const MCInstrDesc &MCID = TII->get(AArch64::ADDXri);
841                                             int64_t Offset) const {
851   const MachineFunction *MF = MI.getParent()->getParent();
852   const AArch64InstrInfo *TII =
864                                     const AArch64InstrInfo *TII) {
889     const StackOffset &Offset, SmallVectorImpl<uint64_t> &Ops) const {
917                                               RegScavenger *RS) const {
923   const MachineFrameInfo &MFI = MF.getFrameInfo();
924   const AArch64InstrInfo *TII =
926   const AArch64FrameLowering *TFI = getFrameLowering(MF);
958     const AArch64FunctionInfo *AFI = MF.getInfo<AArch64FunctionInfo>();
1008 unsigned AArch64RegisterInfo::getRegPressureLimit(const TargetRegisterClass *RC,
1009                                                   MachineFunction &MF) const {
1010   const AArch64FrameLowering *TFI = getFrameLowering(MF);
1056   const MachineFunction &MF) const {
1057   const auto &MFI = MF.getFrameInfo();
1067     MachineInstr *MI, const TargetRegisterClass *SrcRC, unsigned SubReg,
1068     const TargetRegisterClass *DstRC, unsigned DstSubReg,
1069     const TargetRegisterClass *NewRC, LiveIntervals &LIS) const {
1081   auto IsCoalescerBarrier = [](const MachineInstr &MI) {
1117     MCRegister R) const {