Lines Matching defs:LogicOpcode

5763   unsigned LogicOpcode = N->getOpcode();
5765   assert(ISD::isBitwiseLogicOp(LogicOpcode) && "Expected logic opcode");
5793         !TLI.isOperationLegalOrCustom(LogicOpcode, XVT))
5799         LegalTypes && !TLI.isTypeDesirableForOp(LogicOpcode, XVT))
5802     SDValue Logic = DAG.getNode(LogicOpcode, DL, XVT, X, Y);
5818     if (LegalOperations && !TLI.isOperationLegal(LogicOpcode, XVT))
5826     SDValue Logic = DAG.getNode(LogicOpcode, DL, XVT, X, Y);
5838     SDValue Logic = DAG.getNode(LogicOpcode, DL, XVT, X, Y);
5847     SDValue Logic = DAG.getNode(LogicOpcode, DL, XVT, X, Y);
5861     SDValue Logic0 = DAG.getNode(LogicOpcode, DL, VT, X, Y);
5862     SDValue Logic1 = DAG.getNode(LogicOpcode, DL, VT, X1, Y1);
5879       SDValue Logic = DAG.getNode(LogicOpcode, DL, XVT, X, Y);
5913     if (LogicOpcode == ISD::XOR && !ShOp.isUndef())
5918       SDValue Logic = DAG.getNode(LogicOpcode, DL, VT,
5926     if (LogicOpcode == ISD::XOR && !ShOp.isUndef())
5931       SDValue Logic = DAG.getNode(LogicOpcode, DL, VT, N0.getOperand(1),
6862   unsigned LogicOpcode = N->getOpcode();
6863   assert(ISD::isBitwiseLogicOp(LogicOpcode) &&
6871   if (LogicOp.getOpcode() != LogicOpcode ||
6897   SDValue LogicX = DAG.getNode(LogicOpcode, DL, VT, X0, X1);
6899   return DAG.getNode(LogicOpcode, DL, VT, NewShift, Z);
6910   unsigned LogicOpcode = N->getOpcode();
6911   assert(ISD::isBitwiseLogicOp(LogicOpcode) &&
6913   if (LeftHand.getOpcode() != LogicOpcode ||
6914       RightHand.getOpcode() != LogicOpcode)
6936   return DAG.getNode(LogicOpcode, DL, VT, CombinedShifts, W);
9625   unsigned LogicOpcode = LogicOp.getOpcode();
9626   if (LogicOpcode != ISD::AND && LogicOpcode != ISD::OR &&
9627       LogicOpcode != ISD::XOR)
9685   return DAG.getNode(LogicOpcode, DL, VT, NewShift1, NewShift2,