Lines Matching refs:Part

3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
713     for (unsigned Part = 0; Part < NumParts; ++Part) {
715       if (Part == 0) {
719         if (Part == NumParts - 1)
725                              Args[i].Flags[Part], CCInfo)) {
814         for (unsigned Part = 0; Part < NumParts; ++Part)
815           Args[i].Regs[Part] = MRI.createGenericVirtualRegister(NewLLT);
832     for (unsigned Part = 0; Part < NumParts; ++Part) {
833       assert((VA.getLocInfo() != CCValAssign::Indirect || Part == 0) &&
836       Register ArgReg = Args[i].Regs[Part];
838       unsigned Idx = BigEndianPartOrdering ? NumParts - 1 - Part : Part;
840       const ISD::ArgFlagsTy Flags = Args[i].Flags[Part];
867         MIRBuilder.buildStore(Args[i].OrigRegs[Part], PointerToStackReg,
897           Handler.assignValueToAddress(Args[i], Part, StackAddr, MemTy, MPO,
940         Handler.assignValueToReg(ArgReg, ThisReturnRegs[Part], VA);