History log of /llvm-project/mlir/lib/Dialect/XeGPU/IR/XeGPUDialect.cpp (Results 1 – 11 of 11)
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Revision tags: llvmorg-21-init, llvmorg-19.1.7, llvmorg-19.1.6, llvmorg-19.1.5, llvmorg-19.1.4, llvmorg-19.1.3, llvmorg-19.1.2
# 9fa55ec3 02-Oct-2024 Petr Kurapov <petr.a.kurapov@intel.com>

[MLIR][XeGPU] Add sg_map attribute to support Work Item level semanti… (#110876)

Bring back #108864


# a7b6fdaf 02-Oct-2024 Chao Chen <chao.chen@intel.com>

Revert "[MLIR][XeGPU] Add sg_map attribute to support Work Item level semantics" (#110871)

Reverts #108864 since it breaks compilation


# 3ca5d808 02-Oct-2024 Petr Kurapov <petr.a.kurapov@intel.com>

[MLIR][XeGPU] Add sg_map attribute to support Work Item level semantics (#108864)

The PR adds an attribute (sg_map) describing the distribution of
computation among work items for xegpu operations

[MLIR][XeGPU] Add sg_map attribute to support Work Item level semantics (#108864)

The PR adds an attribute (sg_map) describing the distribution of
computation among work items for xegpu operations to be used in lowering
passes. The map is attached to the tensor descriptor, so the constructor
and the type are updated. Tests check the custom parser & printer. The
attribute is optional now, so no other changes required.
The complete description of the attribute can be found
[here](https://github.com/intel/mlir-extensions/blob/main/docs/rfcs/XeGPU.md#xegpu-attributes-to-support-work-item-level-semantics).

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Revision tags: llvmorg-19.1.1
# 8b5e8414 24-Sep-2024 Chao Chen <chao.chen@intel.com>

[MLIR][XeGPU] Updates XeGPU TensorDescAttr and Refine Gather/Scatter definition (#109675)

Bring back #109144 with fixes to VectorToXeGPU


# 09e94d09 23-Sep-2024 Chao Chen <116223022+chencha3@users.noreply.github.com>

Revert "[MLIR][XeGPU] Updates XeGPU TensorDescAttr and Refine Gather/Scatter definition. " (#109666)

Reverts llvm/llvm-project#109144


# 21627236 23-Sep-2024 Chao Chen <116223022+chencha3@users.noreply.github.com>

[MLIR][XeGPU] Updates XeGPU TensorDescAttr and Refine Gather/Scatter definition. (#109144)

The PR makes the following refine changes to the XeGPU dialect.
1. Separated the old `TensorDescAttr` in

[MLIR][XeGPU] Updates XeGPU TensorDescAttr and Refine Gather/Scatter definition. (#109144)

The PR makes the following refine changes to the XeGPU dialect.
1. Separated the old `TensorDescAttr` into two independent attributes: `BlockTensorDescAttr` and `ScatterTensorDescAttr`
2. Renamed the `MemoryScopeAttr` to `MemorySpaceAttr` and updated the enumeration value for shared memory following OpenCL standard.
3. Introduced `transpose` UnitAttr to `StoreScatterOp`and `LoadGatherOp`
4. Added memory space check for `CreateNdDesc` and `CreateDesc` op, as well as valid and invalid test cases for them.

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Revision tags: llvmorg-19.1.0, llvmorg-19.1.0-rc4, llvmorg-19.1.0-rc3, llvmorg-19.1.0-rc2, llvmorg-19.1.0-rc1, llvmorg-20-init, llvmorg-18.1.8, llvmorg-18.1.7, llvmorg-18.1.6, llvmorg-18.1.5, llvmorg-18.1.4
# b01879ec 16-Apr-2024 Chao Chen <116223022+chencha3@users.noreply.github.com>

[MLIR][XeGPU] Add XeGPU scattered ops (#86594)

- Extended TensorDescAttr with scattered attribute
- Add scattered ops: CreateDescOp, PrefetchOp, LoadGatherOp,
StoreScatterOp, UpdateOffsetOp
- Add

[MLIR][XeGPU] Add XeGPU scattered ops (#86594)

- Extended TensorDescAttr with scattered attribute
- Add scattered ops: CreateDescOp, PrefetchOp, LoadGatherOp,
StoreScatterOp, UpdateOffsetOp
- Add a block op: UpdateNdOffsetOp

---------

Co-authored-by: Mehdi Amini <joker.eph@gmail.com>
Co-authored-by: Adam Siemieniuk <adam.siemieniuk@intel.com>

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Revision tags: llvmorg-18.1.3
# 61b24c61 20-Mar-2024 Chao Chen <116223022+chencha3@users.noreply.github.com>

[MLIR][XeGPU] Adding XeGPU 2d block operators (#85804)

This PR adds XeGPU 2D block operators. It contains:
1. TensorDescType and TensorDescAttr definitions
2. MemoryScopeAttr and CacheHintAttr def

[MLIR][XeGPU] Adding XeGPU 2d block operators (#85804)

This PR adds XeGPU 2D block operators. It contains:
1. TensorDescType and TensorDescAttr definitions
2. MemoryScopeAttr and CacheHintAttr definitions which are used by
TensorDescAttr.
3. CreateNdDescOp, PrefetchNdOp, LoadNdOp, and StoreNdOp definitions,
and their corresponding testcases for illustration.

It cherry-picks daebe5c4f27ba140ac8d13abf41e3fe4db72b91a with asan fix.

---------

Co-authored-by: Mehdi Amini <joker.eph@gmail.com>

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Revision tags: llvmorg-18.1.2
# 8d142043 18-Mar-2024 Balaji V. Iyer <43187390+bviyer@users.noreply.github.com>

Revert "[MLIR][XeGPU] Adding XeGPU 2d block operators (#84692)" (#85653)

This reverts commit daebe5c4f27ba140ac8d13abf41e3fe4db72b91a.

This commit causes the following asan issue:

```
<snip>/

Revert "[MLIR][XeGPU] Adding XeGPU 2d block operators (#84692)" (#85653)

This reverts commit daebe5c4f27ba140ac8d13abf41e3fe4db72b91a.

This commit causes the following asan issue:

```
<snip>/llvm-project/build/bin/mlir-opt <snip>/llvm-project/mlir/test/Dialect/XeGPU/XeGPUOps.mlir | <snip>/llvm-project/build/bin/FileCheck <snip>/llvm-project/mlir/test/Dialect/XeGPU/XeGPUOps.mlir
# executed command: <snip>/llvm-project/build/bin/mlir-opt <snip>/llvm-project/mlir/test/Dialect/XeGPU/XeGPUOps.mlir
# .---command stderr------------
# | =================================================================
# | ==2772558==ERROR: AddressSanitizer: stack-use-after-return on address 0x7fd2c2c42b90 at pc 0x55e406d54614 bp 0x7ffc810e4070 sp 0x7ffc810e4068
# | READ of size 8 at 0x7fd2c2c42b90 thread T0
# | #0 0x55e406d54613 in operator()<long int const*> /usr/include/c++/13/bits/predefined_ops.h:318
# | #1 0x55e406d54613 in __count_if<long int const*, __gnu_cxx::__ops::_Iter_pred<mlir::verifyListOfOperandsOrIntegers(Operation*, llvm::StringRef, unsigned int, llvm::ArrayRef<long int>, ValueRange)::<lambda(int64_t)> > > /usr/include/c++/13/bits/stl_algobase.h:2125
# | #2 0x55e406d54613 in count_if<long int const*, mlir::verifyListOfOperandsOrIntegers(Operation*,
...
```

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# daebe5c4 18-Mar-2024 Chao Chen <116223022+chencha3@users.noreply.github.com>

[MLIR][XeGPU] Adding XeGPU 2d block operators (#84692)

Hi @joker-eph, This PR adds XeGPU 2D block operators. It contains:
1. `TensorDescType` and `TensorDescAttr` definitions
2. `MemoryScopeAttr`

[MLIR][XeGPU] Adding XeGPU 2d block operators (#84692)

Hi @joker-eph, This PR adds XeGPU 2D block operators. It contains:
1. `TensorDescType` and `TensorDescAttr` definitions
2. `MemoryScopeAttr` and `CacheHintAttr` definitions which are used by
`TensorDescAttr`.
3. `CreateNdDescOp`, `PrefetchNdOp`, `LoadNdOp`, and `StoreNdOp`
definitions, and their corresponding testcases for illustration.

---------

Co-authored-by: Mehdi Amini <joker.eph@gmail.com>

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Revision tags: llvmorg-18.1.1
# 5669660f 07-Mar-2024 Chao Chen <116223022+chencha3@users.noreply.github.com>

[MLIR] XeGPU dialect for Intel GPU - core definitions and base classes (#78483)

This PR follows our previous [RFC
](https://discourse.llvm.org/t/rfc-add-xegpu-dialect-for-intel-gpus/75723)
to add

[MLIR] XeGPU dialect for Intel GPU - core definitions and base classes (#78483)

This PR follows our previous [RFC
](https://discourse.llvm.org/t/rfc-add-xegpu-dialect-for-intel-gpus/75723)
to add XeGPU dialect definition for Intel GPUs. It contains dialect,
type, attributes and operators definitions, as well as testcases for
semantic checks. The lowering and optimization passes will be issued
with separated passes.

---------

Co-authored-by: Mehdi Amini <joker.eph@gmail.com>

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