[RISCV] Support zext.h mnemonic with Zbkb. (#96821)

Zbkb adds generic pack insructions. The zext.h encodings from Zbb are
subsets of the generic encodings with rs2=x0. zext.h is pack on RV32 and
p

[RISCV] Support zext.h mnemonic with Zbkb. (#96821)

Zbkb adds generic pack insructions. The zext.h encodings from Zbb are
subsets of the generic encodings with rs2=x0. zext.h is pack on RV32 and
packw on RV64.

Previously we only supported zext.h as a single instruction mnemonic in
the assembler when Zbb was enabled. Otherwise we would emit it as 2
shifts. This patches recognizes it when either Zbkb or Zbb is enabled.

This patch also enables the zext.h isel patterns when Zbkb is enabled
without Zbb.

show more ...

[RISCV] Add more packh patterns.

[RISCV] Teach getRegAllocationHints about compressible SRAI/SRLI.

Similar to previous patches for ADDI/ADDIW/SLLI/ADD, but restricted
to only cases where the register is x8-x15(GPRC reg class).

I'v

[RISCV] Teach getRegAllocationHints about compressible SRAI/SRLI.

Similar to previous patches for ADDI/ADDIW/SLLI/ADD, but restricted
to only cases where the register is x8-x15(GPRC reg class).

I've restricted it so that we can be precise about whether the
resulting instruction would be compressible. Changing the register
allocation may make some other instruction not compressible so we
should try to be accurate.

Reviewed By: asb

Differential Revision: https://reviews.llvm.org/D138740

show more ...

[RISCV] Use register allocation hints to improve use of compressed instructions.

Compressed instructions usually require one of the source registers
to also be the source register. The register allo

[RISCV] Use register allocation hints to improve use of compressed instructions.

Compressed instructions usually require one of the source registers
to also be the source register. The register allocator doesn't have
that bias on its own.

This patch adds register allocation hints to introduce this bias.
I've started with ADDI, ADDIW, and SLLI. These all have a 5-bit
field for the register. If the source and dest register are the
same they are guaranteed to compress as long as the immediate is
also 6 bits.

This code was inspired by similar code from the SystemZ target.

Reviewed By: reames

Differential Revision: https://reviews.llvm.org/D138242

show more ...

[RISCV] Remove old test case. NFC

This seemed to be testing a pattern for an RV64 Zbp instruction, but
on RV32. On RV32, it's just swizzling registers so isn't very
interesting.

[RISCV] Improve use of PACK instruction on rv64.

Handle the case where the lower bits come from a zero extending
load or other operation with known zero bits.

[RISCV] Add another PACKH pattern.

This handles the case where the upper bits are zeroed with an AND
after the OR.

[RISCV] Improve PACKH instruction selection

Handle AssertZExt in addition to AND.

[RISCV] Improve selection of PACKW.

Use hasAllWUsers to check if the upper bits are ignored so we can
use PACKW even when no sign_extend_inreg is present before the OR.

[RISCV] Improve selection of PACK/PACKW for AssertZExt input.

[RISCV] Remove support for the unratified Zbp extension.

This extension does not appear to be on its way to ratification.

Still need some follow up to simplify the RISCVISD nodes.