[RISCV] Enable bidirectional scheduling and tracking register pressure (#115445)


This is based on other targets like PPC/AArch64 and some experiments.

This PR will only enable bidirectional schedu

[RISCV] Enable bidirectional scheduling and tracking register pressure (#115445)


This is based on other targets like PPC/AArch64 and some experiments.

This PR will only enable bidirectional scheduling and tracking register
pressure.

Disclaimer: I haven't tested it on many cores, maybe we should make
some options being features. I believe downstreams must have tried
this before, so feedbacks are welcome.

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[RISCV] Improve hasAllNBitUsers for users of SLLI.

We can increase the number of Bits passes to the users by adding
the shift amount.

[RISCV] Improve constant materialisation for stores of i8 negative constants (#92131)

This follows the same pattern as 20e62658735a1b03ecadc. Although we
can't reduce the number of instructions use

[RISCV] Improve constant materialisation for stores of i8 negative constants (#92131)

This follows the same pattern as 20e62658735a1b03ecadc. Although we
can't reduce the number of instructions used, if we are able to use a
sign-extended 6-bit immediate then the 16-bit c.li instruction can be
selected (thus saving code size). Although this _could_ be gated so it
only happens if C is enabled, I've opted not to because at worst it's
neutral and it doesn't seem helpful to add unnecessary divergence
between the RVC and non-RVC paths.

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[RISCV][test] Precommit tests for byte store of -1

Although we can't reduce the number of instructions, if we selected `li
rd, -1` instead then this could be encoded in a 16-bit instruction.

[RISCV] Improve use of BSETI/BCLRI in constant materialization. (#91546)

We failed to use BSETI when bit 31 was set and a few bits above bit 31
were set. We also failed to use multiple BSETI when t

[RISCV] Improve use of BSETI/BCLRI in constant materialization. (#91546)

We failed to use BSETI when bit 31 was set and a few bits above bit 31
were set. We also failed to use multiple BSETI when the low 32 bits were
zero.

I've removed the special cases for constants 0x80000000-0xffffffff and
wrote a more generic algorithm for BSETI.

I've rewritten the BCLRI handling to be similar to the new BSETI
algorithm. This picks up cases where bit 31 is 0 and only a few high
bits are 0.

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[RISCV] Add another missed Zbs constant materialization test. NFC

This can be LI+BCLRI+BCLRI.

[RISCV] Add tests where we could use Zbs instructions in constant materialization. NFC

[RISCV] Remove old FIXMEs from test. NFC

[RISCV] Add an experimental pseudoinstruction to represent a rematerializable constant materialization sequence. (#69983)

Rematerialization during register allocation is currently limited to a
sing

[RISCV] Add an experimental pseudoinstruction to represent a rematerializable constant materialization sequence. (#69983)

Rematerialization during register allocation is currently limited to a
single instruction with no inputs.

This patch introduces a pseudoinstruction that represents the
materialization of a constant. I've started with a sequence of 2
instructions for now, which covers at least the common LUI+ADDI(W) case.
This instruction will be expanded into real instructions immediately
after register allocation using a new pass. This gives the post-RA
scheduler a chance to separate the 2 instructions to improve ILP.

I believe this matches the approach used by AArch64.

Unfortunately, this loses some CSE opportunies when an LUI value is used
by multiple constants with different LSBs.

This feature is off by default and a new backend command line option is
added to enable it for testing.

This avoids the spill and reloads reported in #69586.

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[RISCV] Strip W suffix from ADDIW (#68425)

The motivation of this change is simply to reduce test duplication. As
can be seen in the (massive) test delta, we have many tests whose output
differ on

[RISCV] Strip W suffix from ADDIW (#68425)

The motivation of this change is simply to reduce test duplication. As
can be seen in the (massive) test delta, we have many tests whose output
differ only due to the use of addi on rv32 vs addiw on rv64 when the
high bits are don't care.

As an aside, we don't need to worry about the non-zero immediate
restriction on the compressed variants because we're not directly
forming the compressed variants. If we happen to get a zero immediate
for the ADDI, then either a later optimization will strip the useless
instruction or the encoder is responsible for not compressing the
instruction.

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[RISCV] Generalize the (ADD (SLLI X, 32), X) special case in constant materialization. (#66931)

We don't have to limit ourselves to a shift amount of 32. We can support
other shift amounts that mak

[RISCV] Generalize the (ADD (SLLI X, 32), X) special case in constant materialization. (#66931)

We don't have to limit ourselves to a shift amount of 32. We can support
other shift amounts that make the upper 32 bits line up.

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[RISCV] Improve constant materialization by using a sequence that end… (#66943)

…s with 2 addis in some cases.

If the lower 13 bits are something like 0x17ff, we can first materialize
it as 0x18

[RISCV] Improve constant materialization by using a sequence that end… (#66943)

…s with 2 addis in some cases.

If the lower 13 bits are something like 0x17ff, we can first materialize
it as 0x1800 followed by an addi to subtract a small offset. This might
be cheaper to materialize since the constant ending in 0x1800 can use a
simm12 immediate for its final addi.

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Recommmit "[RISCV] Improve contant materialization to end with 'not' if the cons… (#66950)"

With MC test updates.

Original commit message

We can invert the value and treat it as if it had leading

Recommmit "[RISCV] Improve contant materialization to end with 'not' if the cons… (#66950)"

With MC test updates.

Original commit message

We can invert the value and treat it as if it had leading zeroes.

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Revert "[RISCV] Improve contant materialization to end with 'not' if the cons… (#66950)"

This reverts commit a8b8e9476451e125e81bd24fbde6605246c59a0e.

Forgot to update MC tests.

[RISCV] Improve contant materialization to end with 'not' if the cons… (#66950)

…tant has leading ones.

We can invert the value and treat it as if it had leading zeroes.

[RISCV] Teach MatInt to use (ADD_UW X, (SLLI X, 32)) to materialize some constants.

If the high and low 32 bits are the same, we try to use
(ADD X, (SLLI X, 32)) but that only works if bit 31 is cle

[RISCV] Teach MatInt to use (ADD_UW X, (SLLI X, 32)) to materialize some constants.

If the high and low 32 bits are the same, we try to use
(ADD X, (SLLI X, 32)) but that only works if bit 31 is clear since
the low 32 bits will be sign extended.

If we have Zba we can use add.uw to zero the sign extended bits.

Reviewed By: reames, wangpc

Differential Revision: https://reviews.llvm.org/D159253

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[RISCV] Don't use (ADD (SLLI C, 32), C) to materialize constants when optimizing for size.

Addresses post-commit feedback from D152236.

Reviewed By: asb, dtcxzyw

Differential Revision: https://rev

[RISCV] Don't use (ADD (SLLI C, 32), C) to materialize constants when optimizing for size.

Addresses post-commit feedback from D152236.

Reviewed By: asb, dtcxzyw

Differential Revision: https://reviews.llvm.org/D152602

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[RISCV] Add vendor-defined XTheadBb (basic bit-manipulation) extension

The vendor-defined XTHeadBb (predating the standard Zbb extension)
extension adds some bit-manipulation extensions with somewha

[RISCV] Add vendor-defined XTheadBb (basic bit-manipulation) extension

The vendor-defined XTHeadBb (predating the standard Zbb extension)
extension adds some bit-manipulation extensions with somewhat similar
semantics as some of the Zbb instructions.

It is supported by the C9xx cores (e.g., found in the wild in the
Allwinner D1) by Alibaba T-Head.

The current (as of this commit) public documentation for XTHeadBb is
available from:
https://github.com/T-head-Semi/thead-extension-spec/releases/download/2.2.2/xthead-2023-01-30-2.2.2.pdf

Support for these instructions has already landed in GNU Binutils:
https://sourceware.org/git/?p=binutils-gdb.git;a=commit;h=8254c3d2c94ae5458095ea6c25446ba89134b9da

Depends on D143036

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D143439

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Revert "[RISCV] Add vendor-defined XTheadBb (basic bit-manipulation) extension"

This reverts commit 19a59099095b3cbc9846e5330de26fca0a44ccbe.

[RISCV] Add vendor-defined XTheadBb (basic bit-manipulation) extension

The vendor-defined XTHeadBb (predating the standard Zbb extension)
extension adds some bit-manipulation extensions with somewha

[RISCV] Add vendor-defined XTheadBb (basic bit-manipulation) extension

The vendor-defined XTHeadBb (predating the standard Zbb extension)
extension adds some bit-manipulation extensions with somewhat similar
semantics as some of the Zbb instructions.

It is supported by the C9xx cores (e.g., found in the wild in the
Allwinner D1) by Alibaba T-Head.

The current (as of this commit) public documentation for XTHeadBb is
available from:
https://github.com/T-head-Semi/thead-extension-spec/releases/download/2.2.2/xthead-2023-01-30-2.2.2.pdf

Support for these instructions has already landed in GNU Binutils:
https://sourceware.org/git/?p=binutils-gdb.git;a=commit;h=8254c3d2c94ae5458095ea6c25446ba89134b9da

Depends on D143036

Differential Revision: https://reviews.llvm.org/D143439

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[RISCV] Convert some tests to opaque pointers (NFC)

[RISCV] Use bseti for 2048 in RISCVMatInt when Zbs is enabled.

2048 requires an LUI and ADDI instruction due to ADDI using a
signed immediate. It can also be done with C.LI+C.SLLI for better
code si

[RISCV] Use bseti for 2048 in RISCVMatInt when Zbs is enabled.

2048 requires an LUI and ADDI instruction due to ADDI using a
signed immediate. It can also be done with C.LI+C.SLLI for better
code size.

With Zbs we can use a single BSETI to have an instruction.

Reorder the checks so that BSETI is checked first, with an extra
qualification to prefer a single LUI or ADDI when possible. I'm
continuing to think about other ways to structure this code, but
this works for now.

Fixes PR59362.

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[RISCV] Use register allocation hints to improve use of compressed instructions.

Compressed instructions usually require one of the source registers
to also be the source register. The register allo

[RISCV] Use register allocation hints to improve use of compressed instructions.

Compressed instructions usually require one of the source registers
to also be the source register. The register allocator doesn't have
that bias on its own.

This patch adds register allocation hints to introduce this bias.
I've started with ADDI, ADDIW, and SLLI. These all have a 5-bit
field for the register. If the source and dest register are the
same they are guaranteed to compress as long as the immediate is
also 6 bits.

This code was inspired by similar code from the SystemZ target.

Reviewed By: reames

Differential Revision: https://reviews.llvm.org/D138242

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[RISCV] Improve constant materialization for cases that can use LUI+ADDI instead of LUI+ADDIW.

It's possible that we have a constant that isn't simm32 so we can't
use LUI+ADDIW, but we can use LUI+A

[RISCV] Improve constant materialization for cases that can use LUI+ADDI instead of LUI+ADDIW.

It's possible that we have a constant that isn't simm32 so we can't
use LUI+ADDIW, but we can use LUI+ADDI. Because ADDI uses a sign
extended constant, it's possible that after subtracting it out, we
end up with a simm32 that maps to LUI.

This patch detects this case after removing Lo12 and before shifting
the value for SLLI.

Reviewed By: luismarques

Differential Revision: https://reviews.llvm.org/D124222

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[RISCV] Teach generateInstSeqImpl to generate BSETI for single bit cases.

If the immediate has one bit set, but isn't a simm32 we can try
the BSETI instruction from Zbs.