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Revision tags: llvmorg-21-init, llvmorg-19.1.7, llvmorg-19.1.6, llvmorg-19.1.5, llvmorg-19.1.4 |
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9122c523 |
| 15-Nov-2024 |
Pengcheng Wang <wangpengcheng.pp@bytedance.com> |
[RISCV] Enable bidirectional scheduling and tracking register pressure (#115445)
This is based on other targets like PPC/AArch64 and some experiments.
This PR will only enable bidirectional schedu
[RISCV] Enable bidirectional scheduling and tracking register pressure (#115445)
This is based on other targets like PPC/AArch64 and some experiments.
This PR will only enable bidirectional scheduling and tracking register
pressure.
Disclaimer: I haven't tested it on many cores, maybe we should make
some options being features. I believe downstreams must have tried
this before, so feedbacks are welcome.
show more ...
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Revision tags: llvmorg-19.1.3, llvmorg-19.1.2, llvmorg-19.1.1, llvmorg-19.1.0, llvmorg-19.1.0-rc4, llvmorg-19.1.0-rc3, llvmorg-19.1.0-rc2, llvmorg-19.1.0-rc1, llvmorg-20-init, llvmorg-18.1.8, llvmorg-18.1.7, llvmorg-18.1.6, llvmorg-18.1.5, llvmorg-18.1.4, llvmorg-18.1.3, llvmorg-18.1.2, llvmorg-18.1.1, llvmorg-18.1.0, llvmorg-18.1.0-rc4, llvmorg-18.1.0-rc3, llvmorg-18.1.0-rc2, llvmorg-18.1.0-rc1 |
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| #
d833b9d6 |
| 29-Jan-2024 |
Alex Bradbury <asb@igalia.com> |
[RISCV] Graduate Zicond to non-experimental (#79811)
The Zicond extension was ratified in the last few months, with no
changes that affect the LLVM implementation. Although there's surely
more tun
[RISCV] Graduate Zicond to non-experimental (#79811)
The Zicond extension was ratified in the last few months, with no
changes that affect the LLVM implementation. Although there's surely
more tuning that could be done about when to select Zicond or not, there
are no known correctness issues. Therefore, we should mark support as
non-experimental.
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Revision tags: llvmorg-19-init, llvmorg-17.0.6, llvmorg-17.0.5, llvmorg-17.0.4, llvmorg-17.0.3, llvmorg-17.0.2, llvmorg-17.0.1, llvmorg-17.0.0, llvmorg-17.0.0-rc4, llvmorg-17.0.0-rc3, llvmorg-17.0.0-rc2, llvmorg-17.0.0-rc1, llvmorg-18-init |
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| #
0fb3ebb2 |
| 13-Jul-2023 |
Mikhail Gudim <mgudim@gmail.com> |
[RISCV] Generalize 'tryFoldSelectIntOp` to other operations.
Currently, only `SUB`, `ADD`, `OR` and `XOR` are covered. This patch
adds `AND`, `SHL`, `SRA`, `SRL`.
Reviewed By: craig.topper
Differen
[RISCV] Generalize 'tryFoldSelectIntOp` to other operations.
Currently, only `SUB`, `ADD`, `OR` and `XOR` are covered. This patch
adds `AND`, `SHL`, `SRA`, `SRL`.
Reviewed By: craig.topper
Differential Revision: https://reviews.llvm.org/D155344
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| #
cb15e657 |
| 17-Jul-2023 |
Mikhail Gudim <mgudim@gmail.com> |
[RISCV] A test for conditional binary ops.
Consider the following pattern:
```
%binop_ = binop %x, %y
%select_ = select %c, %binop_, %x
```
If there is an identity `%identity` operand for `binop`,
[RISCV] A test for conditional binary ops.
Consider the following pattern:
```
%binop_ = binop %x, %y
%select_ = select %c, %binop_, %x
```
If there is an identity `%identity` operand for `binop`, it is possible to transform
the above code to:
```
%opearand = select %c, %y, %identity
%result = binop %x, %operand
```
This transformation is profitable when `%identity` is all zeroes or
ones.
This patch commits a test for such patterns.
Reviewed By: craig.topper
Differential Revision: https://reviews.llvm.org/D155481
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