[InstCombine] Pass a proper context instruction to all of the calls into InstSimplify

Summary: This matches the behavior we already had for compares and makes us consistent everywhere.

Reviewers: d

[InstCombine] Pass a proper context instruction to all of the calls into InstSimplify

Summary: This matches the behavior we already had for compares and makes us consistent everywhere.

Reviewers: dberlin, hfinkel, spatel

Reviewed By: dberlin

Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D33604

llvm-svn: 305049

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[InstCombine][InstSimplify] Use APInt::isNullValue/isOneValue to reduce compiled code for comparing APInts with 0 and 1. NFC

These methods are specifically optimized to only counting leading zeros w

[InstCombine][InstSimplify] Use APInt::isNullValue/isOneValue to reduce compiled code for comparing APInts with 0 and 1. NFC

These methods are specifically optimized to only counting leading zeros without an additional uint64_t compare.

llvm-svn: 304876

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[ValueTracking] Convert most of the calls to computeKnownBits to use the version that returns the KnownBits object.

This continues the changes started when computeSignBit was replaced with this new

[ValueTracking] Convert most of the calls to computeKnownBits to use the version that returns the KnownBits object.

This continues the changes started when computeSignBit was replaced with this new version of computeKnowBits.

Differential Revision: https://reviews.llvm.org/D33431

llvm-svn: 303773

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[InstCombine] Cleanup the interface for overflow checks

Summary:
Fix naming conventions and const correctness.
This completes the changes made in rL303029.

Patch by Yoav Ben-Shalom.

Reviewers: cra

[InstCombine] Cleanup the interface for overflow checks

Summary:
Fix naming conventions and const correctness.
This completes the changes made in rL303029.

Patch by Yoav Ben-Shalom.

Reviewers: craig.topper

Reviewed By: craig.topper

Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D33377

llvm-svn: 303529

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[KnownBits] Use isNegative/isNonNegative to shorten some code. NFC

llvm-svn: 303522

[ValueTracking] Replace all uses of ComputeSignBit with computeKnownBits.

This patch finishes off the conversion of ComputeSignBit to computeKnownBits.

Differential Revision: https://reviews.llvm.o

[ValueTracking] Replace all uses of ComputeSignBit with computeKnownBits.

This patch finishes off the conversion of ComputeSignBit to computeKnownBits.

Differential Revision: https://reviews.llvm.org/D33166

llvm-svn: 303035

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[InstCombine] Merge duplicate functionality between InstCombine and ValueTracking

Summary:
Merge overflow computation for signed add,
appearing both in InstCombine and ValueTracking.

As part of the

[InstCombine] Merge duplicate functionality between InstCombine and ValueTracking

Summary:
Merge overflow computation for signed add,
appearing both in InstCombine and ValueTracking.

As part of the merge,
cleanup the interface for overflow checks in InstCombine.

Patch by Yoav Ben-Shalom.

Reviewers: craig.topper, majnemer

Reviewed By: craig.topper

Subscribers: takuto.ikuta, llvm-commits

Differential Revision: https://reviews.llvm.org/D32946

llvm-svn: 303029

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[InstCombine] add (ashr (shl i32 X, 31), 31), 1 --> and (not X), 1

This is another step towards favoring 'not' ops over random 'xor' in IR:
https://bugs.llvm.org/show_bug.cgi?id=32706

This transfor

[InstCombine] add (ashr (shl i32 X, 31), 31), 1 --> and (not X), 1

This is another step towards favoring 'not' ops over random 'xor' in IR:
https://bugs.llvm.org/show_bug.cgi?id=32706

This transformation may have occurred in longer IR sequences using computeKnownBits,
but that could be much more expensive to calculate.

As the scalar result shows, we do not currently favor 'not' in all cases. The 'not'
created by the transform is transformed again (unnecessarily). Vectors don't have
this problem because vectors are (wrongly) excluded from several other combines.

llvm-svn: 302659

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[InstCombine] add helper function for add X, C folds; NFCI

llvm-svn: 302605

[InstCombine][KnownBits] Use KnownBits better to detect nsw adds

Change checkRippleForAdd from a heuristic to a full check -
if it is provable that the add does not overflow return true, otherwise f

[InstCombine][KnownBits] Use KnownBits better to detect nsw adds

Change checkRippleForAdd from a heuristic to a full check -
if it is provable that the add does not overflow return true, otherwise false.

Patch by Yoav Ben-Shalom

Differential Revision: https://reviews.llvm.org/D32686

llvm-svn: 302093

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[APInt] Add clearSignBit method. Use it and setSignBit in a few places. NFCI

llvm-svn: 301656

InstCombine: Use the new SimplifyQuery versions of Simplify*. Use AssumptionCache, DominatorTree, TargetLibraryInfo everywhere.

llvm-svn: 301464

[ValueTracking] Introduce a KnownBits struct to wrap the two APInts for computeKnownBits

This patch introduces a new KnownBits struct that wraps the two APInt used by computeKnownBits. This allows u

[ValueTracking] Introduce a KnownBits struct to wrap the two APInts for computeKnownBits

This patch introduces a new KnownBits struct that wraps the two APInt used by computeKnownBits. This allows us to treat them as more of a unit.

Initially I've just altered the signatures of computeKnownBits and InstCombine's simplifyDemandedBits to pass a KnownBits reference instead of two separate APInt references. I'll do similar to the SelectionDAG version of computeKnownBits/simplifyDemandedBits as a separate patch.

I've added a constructor that allows initializing both APInts to the same bit width with a starting value of 0. This reduces the repeated pattern of initializing both APInts. Once place default constructed the APInts so I added a default constructor for those cases.

Going forward I would like to add more methods that will work on the pairs. For example trunc, zext, and sext occur on both APInts together in several places. We should probably add a clear method that can be used to clear both pieces. Maybe a method to check for conflicting information. A method to return (Zero|One) so we don't write it out everywhere. Maybe a method for (Zero|One).isAllOnesValue() to determine if all bits are known. I'm sure there are many other methods we can come up with.

Differential Revision: https://reviews.llvm.org/D32376

llvm-svn: 301432

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InstCombine: Fix assert when reassociating fsub with undef

There is logic to track the expected number of instructions
produced. It thought in this case an instruction would
be necessary to negate t

InstCombine: Fix assert when reassociating fsub with undef

There is logic to track the expected number of instructions
produced. It thought in this case an instruction would
be necessary to negate the result, but here it folded
into a ConstantExpr fneg when the non-undef value operand
was cancelled out by the second fsub.

I'm not sure why we don't fold constant FP ops with undef currently,
but I think that would also avoid this problem.

llvm-svn: 301199

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Fix for PR32740 - Invalid floating type, unreachable between r300969 and r301029

The bug was introduced by r301018 "[InstCombine] fadd double (sitofp x), y check that the promotion is valid". The pa

Fix for PR32740 - Invalid floating type, unreachable between r300969 and r301029

The bug was introduced by r301018 "[InstCombine] fadd double (sitofp x), y check that the promotion is valid". The patch didn't expect that fadd can be on vectors not necessarily scalars. Add vector support along with the test.

llvm-svn: 301070

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[InstCombine] fadd double (sitofp x), y check that the promotion is valid

Doing these transformations check that the result of integer addition is representable in the FP type.

(fadd double (sitofp

[InstCombine] fadd double (sitofp x), y check that the promotion is valid

Doing these transformations check that the result of integer addition is representable in the FP type.

(fadd double (sitofp x), fpcst) --> (sitofp (add int x, intcst))
(fadd double (sitofp x), (sitofp y)) --> (sitofp (add int x, y))

This is a fix for https://bugs.llvm.org//show_bug.cgi?id=27036

Reviewed By: andrew.w.kaylor, scanon, spatel

Differential Revision: https://reviews.llvm.org/D31182

llvm-svn: 301018

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[APInt] Rename getSignBit to getSignMask

getSignBit is a static function that creates an APInt with only the sign bit set. getSignMask seems like a better name to convey its functionality. In fact s

[APInt] Rename getSignBit to getSignMask

getSignBit is a static function that creates an APInt with only the sign bit set. getSignMask seems like a better name to convey its functionality. In fact several places use it and then store in an APInt named SignMask.

Differential Revision: https://reviews.llvm.org/D32108

llvm-svn: 300856

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[InstCombine] Support folding a subtract with a constant LHS into a phi node

We currently only support folding a subtract into a select but not a PHI. This fixes that.

I had to fix an assumption in

[InstCombine] Support folding a subtract with a constant LHS into a phi node

We currently only support folding a subtract into a select but not a PHI. This fixes that.

I had to fix an assumption in FoldOpIntoPhi that assumed the PHI node was always in operand 0. Now we pass it in like we do for FoldOpIntoSelect. But we still require some dancing to find the Constant when we create the BinOp or ConstantExpr. This is based code is similar to what we do for selects.

Since I touched all call sites, this also renames FoldOpIntoPhi to foldOpIntoPhi to match coding standards.

Differential Revision: https://reviews.llvm.org/D31686

llvm-svn: 300363

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Fix spelling compliment->complement. Mostly refering to 2s complement. NFC

llvm-svn: 299970

[InstCombine] Use commutable matchers and m_OneUse in visitSub to shorten code. Add missing test cases.

In one case I removed commute handling for a multiply with a constant since we'll eventually g

[InstCombine] Use commutable matchers and m_OneUse in visitSub to shorten code. Add missing test cases.

In one case I removed commute handling for a multiply with a constant since we'll eventually get the constant on the right hand side.

llvm-svn: 299863

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[InstCombine] Use m_c_Add to shorten some code. Add testcases for this fold since they were missing. NFC

llvm-svn: 299853

[InstCombine] Support folding of add instructions with vector constants into select operations

We currently only fold scalar add of constants into selects. This improves this to support vectors too.

[InstCombine] Support folding of add instructions with vector constants into select operations

We currently only fold scalar add of constants into selects. This improves this to support vectors too.

Differential Revision: https://reviews.llvm.org/D31683

llvm-svn: 299847

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[InstCombine] Use commutable and/or/xor matchers to simplify some code

Summary:
This is my first time using the commutable matchers so wanted to make sure I was doing it right.

Are there any other

[InstCombine] Use commutable and/or/xor matchers to simplify some code

Summary:
This is my first time using the commutable matchers so wanted to make sure I was doing it right.

Are there any other matcher tricks to further shrink this? Can we commute the whole match so we don't have to LHS and RHS separately?

Reviewers: davide, spatel

Reviewed By: davide

Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D31680

llvm-svn: 299840

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[InstCombine] Remove testing assert I accidentally left in r299710.

llvm-svn: 299715

[InstCombine] When checking to see if we can turn subtracts of 2^n - 1 into xor, we only need to call computeKnownBits on the RHS not the whole subtract. While there use isMask instead of isPowerOf2(

[InstCombine] When checking to see if we can turn subtracts of 2^n - 1 into xor, we only need to call computeKnownBits on the RHS not the whole subtract. While there use isMask instead of isPowerOf2(C+1)

Calling computeKnownBits on the RHS should allows us to recurse one step further. isMask is equivalent to the isPowerOf2(C+1) except in the case where C is all ones. But that was already handled earlier by creating a not which is an Xor with all ones. So this should be fine.

llvm-svn: 299710

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