Rename mattr names for AVX-512 to from avx-512 -> avx512f, avx-512-pfi -> av512pf, avx-512-cdi -> avx512cd, avx-512-eri->avx512er. This matches better with official docs and what gcc patches appearto

Rename mattr names for AVX-512 to from avx-512 -> avx512f, avx-512-pfi -> av512pf, avx-512-cdi -> avx512cd, avx-512-eri->avx512er. This matches better with official docs and what gcc patches appearto be using. I didn't touch the has* functions or the feature flag names to avoid change the td and lowering file while commits are still happening.

llvm-svn: 188859

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Fix formatting. No functional change.

llvm-svn: 188746

Add AVX-512 and related features to the CPUID detection code.

llvm-svn: 188745

Added encoding prefixes for KNL instructions (EVEX).
Added 512-bit operands printing.
Added instruction formats for KNL instructions.

llvm-svn: 187324

Re-enable AVX detection on x64 platforms.

llvm-svn: 181313

Unbreaking the non-x86 build bots by protecting the AVX test code properly.

llvm-svn: 180992

Correctly testing for AVX support in x86 based off code from Hosts.cpp.

llvm-svn: 180991

This patch adds the X86FixupLEAs pass, which will reduce instruction
latency for certain models of the Intel Atom family, by converting
instructions into their equivalent LEA instructions, when it is

This patch adds the X86FixupLEAs pass, which will reduce instruction
latency for certain models of the Intel Atom family, by converting
instructions into their equivalent LEA instructions, when it is both
useful and possible to do so.

llvm-svn: 180573

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Formatting.

llvm-svn: 178589

Add support of RDSEED defined in AVX2 extension

llvm-svn: 178314

Add ADX CPUID detection

llvm-svn: 178299

For the current Atom processor, the fastest way to handle a call
indirect through a memory address is to load the memory address into
a register and then call indirect through the register.

This pat

For the current Atom processor, the fastest way to handle a call
indirect through a memory address is to load the memory address into
a register and then call indirect through the register.

This patch implements this improvement by modifying SelectionDAG to
force a function address which is a memory reference to be loaded
into a virtual register.

Patch by Sriram Murali.

llvm-svn: 178171

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Add HLE target feature

llvm-svn: 178082

Add PREFETCHW codegen support

- Add 'PRFCHW' feature defined in AVX2 ISA extension

llvm-svn: 178040

Revert r176166 because it broke one of the lit tests.

llvm-svn: 176171

std::string to StringRef.

llvm-svn: 176166

Reinitialize the ivars in the subtarget so that they can be reset with the new features.

llvm-svn: 175336

Temporary revert of 175320.

llvm-svn: 175322

Reinitialize the ivars in the subtarget.

When we're recalculating the feature set of the subtarget, we need to have the
ivars in their initial state.

llvm-svn: 175320

Use the 'target-features' and 'target-cpu' attributes to reset the subtarget features.

If two functions require different features (e.g., `-mno-sse' vs. `-msse') then
we want to honor that, especial

Use the 'target-features' and 'target-cpu' attributes to reset the subtarget features.

If two functions require different features (e.g., `-mno-sse' vs. `-msse') then
we want to honor that, especially during LTO. We can do that by resetting the
subtarget's features depending upon the 'target-feature' attribute.

llvm-svn: 175314

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added basic support for Intel ADX instructions
-feature flag, instructions definitions, test cases

llvm-svn: 175196

Restrict sin/cos optimization to 64-bit only for now. 32-bit is a bit messy and less critical.

llvm-svn: 173987

Teach SDISel to combine fsin / fcos into a fsincos node if the following
conditions are met:
1. They share the same operand and are in the same BB.
2. Both outputs are used.
3. The target has a nativ

Teach SDISel to combine fsin / fcos into a fsincos node if the following
conditions are met:
1. They share the same operand and are in the same BB.
2. Both outputs are used.
3. The target has a native instruction that maps to ISD::FSINCOS node or
the target provides a sincos library call.

Implemented the generic optimization in sdisel and enabled it for
Mac OSX. Also added an additional optimization for x86_64 Mac OSX by
using an alternative entry point __sincos_stret which returns the two
results in xmm0 / xmm1.

rdar://13087969
PR13204

llvm-svn: 173755

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Pad Short Functions for Intel Atom

The current Intel Atom microarchitecture has a feature whereby
when a function returns early then it is slightly faster to execute
a sequence of NOP instructions t

Pad Short Functions for Intel Atom

The current Intel Atom microarchitecture has a feature whereby
when a function returns early then it is slightly faster to execute
a sequence of NOP instructions to wait until the return address is ready,
as opposed to simply stalling on the ret instruction until
the return address is ready.

When compiling for X86 Atom only, this patch will run a pass,
called "X86PadShortFunction" which will add NOP instructions where less
than four cycles elapse between function entry and return.

It includes tests.

This patch has been updated to address Nadav's review comments
- Optimize only at >= O1 and don't do optimization if -Os is set
- Stores MachineBasicBlock* instead of BBNum
- Uses DenseMap instead of std::map
- Fixes placement of braces

Patch by Andy Zhang.

llvm-svn: 171879

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Revert revision 171524. Original message:

URL: http://llvm.org/viewvc/llvm-project?rev=171524&view=rev
Log:
The current Intel Atom microarchitecture has a feature whereby when a function
returns ear

Revert revision 171524. Original message:

URL: http://llvm.org/viewvc/llvm-project?rev=171524&view=rev
Log:
The current Intel Atom microarchitecture has a feature whereby when a function
returns early then it is slightly faster to execute a sequence of NOP
instructions to wait until the return address is ready,
as opposed to simply stalling on the ret instruction
until the return address is ready.

When compiling for X86 Atom only, this patch will run a pass, called
"X86PadShortFunction" which will add NOP instructions where less than four
cycles elapse between function entry and return.

It includes tests.

Patch by Andy Zhang.

llvm-svn: 171603

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