Revision tags: llvmorg-21-init |
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#
48803bc8 |
| 17-Jan-2025 |
Phoebe Wang <phoebe.wang@intel.com> |
[X86][AMX-AVX512][NFC] Remove P from intrinsic and instruction name (#123270)
Ref.: https://cdrdv2.intel.com/v1/dl/getContent/828965
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fbb9d495 |
| 17-Jan-2025 |
Phoebe Wang <phoebe.wang@intel.com> |
[X86][APX] Support APX + AMX-MOVRS/AMX-TRANSPOSE (#123267)
Ref.: https://cdrdv2.intel.com/v1/dl/getContent/784266
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Revision tags: llvmorg-19.1.7 |
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19032bfe |
| 13-Jan-2025 |
Daniel Paoliello <danpao@microsoft.com> |
[aarch64][win] Update Called Globals info when updating Call Site info (#122762)
Fixes the "use after poison" issue introduced by #121516 (see <https://github.com/llvm/llvm-project/pull/121516#issue
[aarch64][win] Update Called Globals info when updating Call Site info (#122762)
Fixes the "use after poison" issue introduced by #121516 (see <https://github.com/llvm/llvm-project/pull/121516#issuecomment-2585912395>).
The root cause of this issue is that #121516 introduced "Called Global" information for call instructions modeling how "Call Site" info is stored in the machine function, HOWEVER it didn't copy the copy/move/erase operations for call site information.
The fix is to rename and update the existing copy/move/erase functions so they also take care of Called Global info.
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Revision tags: llvmorg-19.1.6, llvmorg-19.1.5, llvmorg-19.1.4 |
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813f7c38 |
| 14-Nov-2024 |
Phoebe Wang <phoebe.wang@intel.com> |
[X86][AMX] Support AMX-TRANSPOSE, part 2 (#115660)
Ref.: https://cdrdv2.intel.com/v1/dl/getContent/671368
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1b63f47e |
| 12-Nov-2024 |
Feng Zou <feng.zou@intel.com> |
[X86][AMX] Add AMX FP8 new APIs (#115829)
This is a follow-up to #113850.
Ref.: https://cdrdv2.intel.com/v1/dl/getContent/671368
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f77101ea |
| 12-Nov-2024 |
Malay Sanghi <malay.sanghi@intel.com> |
[X86][AMX] Support AMX-MOVRS (#115151)
Ref.: https://cdrdv2.intel.com/v1/dl/getContent/671368
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eddb79d5 |
| 11-Nov-2024 |
Feng Zou <feng.zou@intel.com> |
[X86][AMX] Support AMX-TF32 (#115625)
Ref.: https://cdrdv2.intel.com/v1/dl/getContent/671368
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dfe43bd1 |
| 09-Nov-2024 |
Kazu Hirata <kazu@google.com> |
[X86] Remove unused includes (NFC) (#115593)
Identified with misc-include-cleaner.
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8f440137 |
| 09-Nov-2024 |
Phoebe Wang <phoebe.wang@intel.com> |
Reland "[X86][AMX] Support AMX-AVX512" (#115581)
Resolve compile fail without SSE2.
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ff225154 |
| 09-Nov-2024 |
Alan Zhao <ayzhao@google.com> |
Revert "[X86][AMX] Support AMX-AVX512" (#115570)
Reverts llvm/llvm-project#114070
Reason: Causes `immintrin.h` to fail to compile if `-msse` and
`-mno-sse2` are passed to clang:
https://github.
Revert "[X86][AMX] Support AMX-AVX512" (#115570)
Reverts llvm/llvm-project#114070
Reason: Causes `immintrin.h` to fail to compile if `-msse` and
`-mno-sse2` are passed to clang:
https://github.com/llvm/llvm-project/pull/114070#issuecomment-2465926700
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58a17e1b |
| 08-Nov-2024 |
Phoebe Wang <phoebe.wang@intel.com> |
[X86][AMX] Support AMX-AVX512 (#114070)
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c72a751d |
| 01-Nov-2024 |
Phoebe Wang <phoebe.wang@intel.com> |
[X86][AMX] Support AMX-TRANSPOSE (#113532)
Ref.: https://cdrdv2.intel.com/v1/dl/getContent/671368
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Revision tags: llvmorg-19.1.3, llvmorg-19.1.2, llvmorg-19.1.1, llvmorg-19.1.0, llvmorg-19.1.0-rc4, llvmorg-19.1.0-rc3, llvmorg-19.1.0-rc2, llvmorg-19.1.0-rc1, llvmorg-20-init, llvmorg-18.1.8, llvmorg-18.1.7, llvmorg-18.1.6, llvmorg-18.1.5, llvmorg-18.1.4, llvmorg-18.1.3, llvmorg-18.1.2, llvmorg-18.1.1 |
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37293e69 |
| 03-Mar-2024 |
Shengchen Kan <shengchen.kan@intel.com> |
[X86][CodeGen] Support long instruction fixup for APX NDD instructions (#83578)
RFC:
https://discourse.llvm.org/t/rfc-support-long-instruction-fixup-for-x86/76539
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265e49d1 |
| 29-Feb-2024 |
Shengchen Kan <shengchen.kan@intel.com> |
[X86][NFC] Lowercase first letter of function names in X86ExpandPseudo.cpp
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273cfd37 |
| 29-Feb-2024 |
Shengchen Kan <shengchen.kan@intel.com> |
[X86][NFC] Avoid duplicated code in X86ExpandPseudo.cpp by using macro GET_EGPR_IF_ENABLED
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Revision tags: llvmorg-18.1.0, llvmorg-18.1.0-rc4, llvmorg-18.1.0-rc3, llvmorg-18.1.0-rc2, llvmorg-18.1.0-rc1, llvmorg-19-init |
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dd6fec5d |
| 22-Jan-2024 |
XinWang10 <108658776+XinWang10@users.noreply.github.com> |
[X86][APX]Support lowering for APX promoted AMX-TILE instructions (#78689)
The enc/dec of promoted AMX-TILE instructions have been supported in
https://github.com/llvm/llvm-project/pull/76210.
Thi
[X86][APX]Support lowering for APX promoted AMX-TILE instructions (#78689)
The enc/dec of promoted AMX-TILE instructions have been supported in
https://github.com/llvm/llvm-project/pull/76210.
This patch support lowering for promoted AMX-TILE instructions and
integrate test to existing tests.
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511ba45a |
| 30-Nov-2023 |
Shengchen Kan <shengchen.kan@intel.com> |
[X86][MC][CodeGen] Support EGPR for KMOV (#73781)
KMOV is essential for copy between k-registers and GPRs.
R16-R31 was added into GPRs in #70958, so we extend KMOV for these new
registers first.
[X86][MC][CodeGen] Support EGPR for KMOV (#73781)
KMOV is essential for copy between k-registers and GPRs.
R16-R31 was added into GPRs in #70958, so we extend KMOV for these new
registers first.
This patch
1. Promotes KMOV instructions from VEX space to EVEX space
2. Emits prefix {evex} for the EVEX variants
3. Prefers EVEX variant than VEX variant in ISEL and optimizations for
better RA
EVEX variants will be compressed to VEX variants by existing EVEX2VEX
pass if no EGPR is used.
RFC:
https://discourse.llvm.org/t/rfc-design-for-apx-feature-egpr-and-ndd-support/73031/4
TAG: llvm-test-suite && CPU2017 can be built with feature egpr
successfully.
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Revision tags: llvmorg-17.0.6, llvmorg-17.0.5, llvmorg-17.0.4, llvmorg-17.0.3, llvmorg-17.0.2, llvmorg-17.0.1, llvmorg-17.0.0, llvmorg-17.0.0-rc4, llvmorg-17.0.0-rc3, llvmorg-17.0.0-rc2, llvmorg-17.0.0-rc1, llvmorg-18-init, llvmorg-16.0.6, llvmorg-16.0.5, llvmorg-16.0.4, llvmorg-16.0.3, llvmorg-16.0.2, llvmorg-16.0.1 |
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e5144d9d |
| 05-Apr-2023 |
David Blaikie <dblaikie@gmail.com> |
Fix a few clang-tidy warnings (container empty checks, function decl/def param naming)
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038b7e6b |
| 31-Mar-2023 |
Xiang1 Zhang <xiang1.zhang@intel.com> |
[X86] Support AMX Complex instructions
Reviewed By: Wang Pengfei
Differential Revision: https://reviews.llvm.org/D147420
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Revision tags: llvmorg-16.0.0, llvmorg-16.0.0-rc4, llvmorg-16.0.0-rc3, llvmorg-16.0.0-rc2, llvmorg-16.0.0-rc1, llvmorg-17-init |
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3b387d10 |
| 24-Jan-2023 |
Stefan Gränitz <stefan.graenitz@gmail.com> |
Lift EHPersonalities from Analysis to IR (NFC)
Computing EH-related information was only relevant for analysis passes so far. Lifting it to IR will allow the IR Verifier to calculate EH funclet colo
Lift EHPersonalities from Analysis to IR (NFC)
Computing EH-related information was only relevant for analysis passes so far. Lifting it to IR will allow the IR Verifier to calculate EH funclet coloring and validate funclet operand bundles in a follow-up step.
Reviewed By: rnk, compnerd
Differential Revision: https://reviews.llvm.org/D138122
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79858d19 |
| 14-Jan-2023 |
Craig Topper <craig.topper@sifive.com> |
[CodeGen][Target] Remove uses of Register::isPhysicalRegister/isVirtualRegister. NFC
Use isPhysical/isVirtual methods.
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Revision tags: llvmorg-15.0.7 |
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#
94c5df8a |
| 01-Dec-2022 |
Xiang1 Zhang <xiang1.zhang@intel.com> |
[AMX] Support AMX-FP16 new intrinsic interface
We support AMX-FP16 isa in https://reviews.llvm.org/D135941 now. The old intrinsic interface need to manually write tile registers. So we support its
[AMX] Support AMX-FP16 new intrinsic interface
We support AMX-FP16 isa in https://reviews.llvm.org/D135941 now. The old intrinsic interface need to manually write tile registers. So we support its new intrinsic interface to let it be able to do register allocation.
Reviewed By: LuoYuanke
Differential Revision: https://reviews.llvm.org/D138987
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Revision tags: llvmorg-15.0.6, llvmorg-15.0.5, llvmorg-15.0.4, llvmorg-15.0.3, working, llvmorg-15.0.2 |
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#
ed8409df |
| 27-Sep-2022 |
Stefan Gränitz <stefan.graenitz@gmail.com> |
[ObjC][ARC] Fix target register for call expanded from CALL_RVMARKER on Windows
Fix regression https://github.com/llvm/llvm-project/issues/56952 for Clang CodeGen on Windows. In the Windows ABI the
[ObjC][ARC] Fix target register for call expanded from CALL_RVMARKER on Windows
Fix regression https://github.com/llvm/llvm-project/issues/56952 for Clang CodeGen on Windows. In the Windows ABI the instruction sequence that is expanded from CALL_RVMARKER should use RCX as target register and not RDI.
Reviewed By: rnk, fhahn
Differential Revision: https://reviews.llvm.org/D134441
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Revision tags: llvmorg-15.0.1, llvmorg-15.0.0, llvmorg-15.0.0-rc3, llvmorg-15.0.0-rc2, llvmorg-15.0.0-rc1, llvmorg-16-init, llvmorg-14.0.6, llvmorg-14.0.5, llvmorg-14.0.4, llvmorg-14.0.3, llvmorg-14.0.2, llvmorg-14.0.1, llvmorg-14.0.0, llvmorg-14.0.0-rc4, llvmorg-14.0.0-rc3, llvmorg-14.0.0-rc2 |
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#
cff5bef9 |
| 15-Feb-2022 |
Sami Tolvanen <samitolvanen@google.com> |
KCFI sanitizer
The KCFI sanitizer, enabled with `-fsanitize=kcfi`, implements a forward-edge control flow integrity scheme for indirect calls. It uses a !kcfi_type metadata node to attach a type ide
KCFI sanitizer
The KCFI sanitizer, enabled with `-fsanitize=kcfi`, implements a forward-edge control flow integrity scheme for indirect calls. It uses a !kcfi_type metadata node to attach a type identifier for each function and injects verification code before indirect calls.
Unlike the current CFI schemes implemented in LLVM, KCFI does not require LTO, does not alter function references to point to a jump table, and never breaks function address equality. KCFI is intended to be used in low-level code, such as operating system kernels, where the existing schemes can cause undue complications because of the aforementioned properties. However, unlike the existing schemes, KCFI is limited to validating only function pointers and is not compatible with executable-only memory.
KCFI does not provide runtime support, but always traps when a type mismatch is encountered. Users of the scheme are expected to handle the trap. With `-fsanitize=kcfi`, Clang emits a `kcfi` operand bundle to indirect calls, and LLVM lowers this to a known architecture-specific sequence of instructions for each callsite to make runtime patching easier for users who require this functionality.
A KCFI type identifier is a 32-bit constant produced by taking the lower half of xxHash64 from a C++ mangled typename. If a program contains indirect calls to assembly functions, they must be manually annotated with the expected type identifiers to prevent errors. To make this easier, Clang generates a weak SHN_ABS `__kcfi_typeid_<function>` symbol for each address-taken function declaration, which can be used to annotate functions in assembly as long as at least one C translation unit linked into the program takes the function address. For example on AArch64, we might have the following code:
``` .c: int f(void); int (*p)(void) = f; p();
.s: .4byte __kcfi_typeid_f .global f f: ... ```
Note that X86 uses a different preamble format for compatibility with Linux kernel tooling. See the comments in `X86AsmPrinter::emitKCFITypeId` for details.
As users of KCFI may need to locate trap locations for binary validation and error handling, LLVM can additionally emit the locations of traps to a `.kcfi_traps` section.
Similarly to other sanitizers, KCFI checking can be disabled for a function with a `no_sanitize("kcfi")` function attribute.
Relands 67504c95494ff05be2a613129110c9bcf17f6c13 with a fix for 32-bit builds.
Reviewed By: nickdesaulniers, kees, joaomoreira, MaskRay
Differential Revision: https://reviews.llvm.org/D119296
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#
a79060e2 |
| 24-Aug-2022 |
Sami Tolvanen <samitolvanen@google.com> |
Revert "KCFI sanitizer"
This reverts commit 67504c95494ff05be2a613129110c9bcf17f6c13 as using PointerEmbeddedInt to store 32 bits breaks 32-bit arm builds.
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