WebAssembly: don't optimize frameindex store

The previous code was incorrect (can't getReg a frameindex). We could instead optimize it to reduce tree height, but I'm not sure that's worthwhile yet b

WebAssembly: don't optimize frameindex store

The previous code was incorrect (can't getReg a frameindex). We could instead optimize it to reduce tree height, but I'm not sure that's worthwhile yet because we then try to eliminate the frameindex.

This patch also fixes frame index elimination for operations which may load or store: it used to assume the base was operand 2 and immediate offset operand 1. That's not true for stores, where they're 4 and 3.

llvm-svn: 259305

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[WebAssembly] Omit no-op adds for non-mem uses of FrameIndex

Differential Revision: http://reviews.llvm.org/D16554

llvm-svn: 258872

[WebAssembly] Minor code formatting cleanups. NFC.

llvm-svn: 258692

[WebAssembly] Use the templated form of MachineFunction::getSubtarget(). NFC.

llvm-svn: 258126

[WebAssembly] Support combining GEP and FrameIndex offsets in memory operand offset field

Previously we only supported putting the FI into memory operand offset
fields if there was nothing there alr

[WebAssembly] Support combining GEP and FrameIndex offsets in memory operand offset field

Previously we only supported putting the FI into memory operand offset
fields if there was nothing there already. Now combine them.

Differential Revision: http://reviews.llvm.org/D15941

llvm-svn: 257084

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[WebAssembly] Implement prolog/epilog insertion and FrameIndex elimination

Summary:
Use the SP32 physical register as the base for FrameIndex
lowering. Update it and the __stack_pointer global var

[WebAssembly] Implement prolog/epilog insertion and FrameIndex elimination

Summary:
Use the SP32 physical register as the base for FrameIndex
lowering. Update it and the __stack_pointer global var in the prolog and
epilog. Extend the mapping of virtual registers to wasm locals to
include the physical registers.

Rather than modify the target-independent PrologEpilogInserter (which
asserts that there are no virtual registers left) include a
slightly-modified copy for Wasm that does not have this assertion and
only clears the virtual registers if scavenging was needed (which of
course it isn't for wasm).

Differential Revision: http://reviews.llvm.org/D15344

llvm-svn: 255392

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[WebAssembly] Initial varargs support.

Full varargs support will depend on prologue/epilogue support, but this patch
gets us started with most of the basic infrastructure.

Differential Revision: ht

[WebAssembly] Initial varargs support.

Full varargs support will depend on prologue/epilogue support, but this patch
gets us started with most of the basic infrastructure.

Differential Revision: http://reviews.llvm.org/D15231

llvm-svn: 254799

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[WebAssembly] Minor clang-format and selected clang-tidy cleanups. NFC.

llvm-svn: 254267

[WebAssembly] Clean up several FIXME comments.

llvm-svn: 254079

Targets: commonize some stack realignment code

This patch does the following:
* Fix FIXME on `needsStackRealignment`: it is now shared between multiple targets, implemented in `TargetRegisterInfo`,

Targets: commonize some stack realignment code

This patch does the following:
* Fix FIXME on `needsStackRealignment`: it is now shared between multiple targets, implemented in `TargetRegisterInfo`, and isn't `virtual` anymore. This will break out-of-tree targets, silently if they used `virtual` and with a build error if they used `override`.
* Factor out `canRealignStack` as a `virtual` function on `TargetRegisterInfo`, by default only looks for the `no-realign-stack` function attribute.

Multiple targets duplicated the same `needsStackRealignment` code:
- Aarch64.
- ARM.
- Mips almost: had extra `DEBUG` diagnostic, which the default implementation now has.
- PowerPC.
- WebAssembly.
- x86 almost: has an extra `-force-align-stack` option, which the default implementation now has.

The default implementation of `needsStackRealignment` used to just return `false`. My current patch changes the behavior by simply using the above shared behavior. This affects:
- AMDGPU
- BPF
- CppBackend
- MSP430
- NVPTX
- Sparc
- SystemZ
- XCore
- Out-of-tree targets
This is a breaking change! `make check` passes.

The only implementation of the `virtual` function (besides the slight different in x86) was Hexagon (which did `MF.getFrameInfo()->getMaxAlignment() > 8`), and potentially some out-of-tree targets. Hexagon now uses the default implementation.

`needsStackRealignment` was being overwritten in `<Target>GenRegisterInfo.inc`, to return `false` as the default also did. That was odd and is now gone.

Reviewers: sunfish

Subscribers: aemerson, llvm-commits, jfb

Differential Revision: http://reviews.llvm.org/D11160

llvm-svn: 242727

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WebAssembly: basic instructions todo, and basic register info.

Summary:
This code is based on AArch64 for modern backend good practice, and NVPTX for
virtual ISA concerns.

Reviewers: sunfish

Subsc

WebAssembly: basic instructions todo, and basic register info.

Summary:
This code is based on AArch64 for modern backend good practice, and NVPTX for
virtual ISA concerns.

Reviewers: sunfish

Subscribers: aemerson, llvm-commits, jfb

Differential Revision: http://reviews.llvm.org/D11070

llvm-svn: 241923

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[WebAssembly] Initial WebAssembly backend

This WebAssembly backend is just a skeleton at this time and is not yet
functional.

llvm-svn: 241022