[RISCV][GISel] Add FCLASS to onlyUsesFP for register bank selection (#118021)

Bug fix FCLASS instruction in RISCV. The bug is due the fact that FCLASS
has an input float register and output GPR thi

[RISCV][GISel] Add FCLASS to onlyUsesFP for register bank selection (#118021)

Bug fix FCLASS instruction in RISCV. The bug is due the fact that FCLASS
has an input float register and output GPR this caused reg bank select
regression.

show more ...

[RISCV][GISel] Custom promote s32 G_FPTOSI/FPTOUI on RV64. (#115268)

I plan to make i32 an illegal type for RV64 to match SelectionDAG and to
remove i32 from the GPR register class.

[RISCV][GISEL] regbankselect for G_SPLAT_VECTOR (#110744)

[RISCV][GISel] Slightly simplify the regbank selection for G_LOAD/STORE. NFC (#101431)

Merge the isVector early out with the previous check for isVector.

[GISEL][RISCV] RegBank Select for Scalable Vector Load/Store (#99932)

This patch supports GlobalISel for register bank selection for scalable vector
load and store instructions in RISC-V

[GISel][TableGen] Generate getRegBankFromRegClass (#99896)

Generating the mapping from a register class to a register bank is
complex:
- there can be lots of register classes
- the mapping may be

[GISel][TableGen] Generate getRegBankFromRegClass (#99896)

Generating the mapping from a register class to a register bank is
complex:
- there can be lots of register classes
- the mapping may be ambiguos
- a register class can span several register banks (e.g. a register
class containing all registers)
- the type information is not enough to decide which register bank to
map to (e.g. a register class containing floating point and vector
registers, and all register can represent a f64 value)

The approach taken here is to encode the register banks in an array
indexed by the ID of the register class. To save space, the entries are
packed into chunks of size 2^n.

show more ...

[RISCV][GISel] Support fcmp and fclass for Zfh. (#96696)

[RISCV] Add FPR16 regbank and start legalizing f16 operations for Zfh. (#96582)

Revert "Intrinsic: introduce minimumnum and maximumnum (#93841)"

As far as I can tell, this pull request was not approved, and
did not go through an RFC on discourse.

This reverts commit 8988148003

Revert "Intrinsic: introduce minimumnum and maximumnum (#93841)"

As far as I can tell, this pull request was not approved, and
did not go through an RFC on discourse.

This reverts commit 89881480030f48f83af668175b70a9798edca2fb.
This reverts commit 225d8fc8eb24fb797154c1ef6dcbe5ba033142da.

show more ...

Intrinsic: introduce minimumnum and maximumnum (#93841)

Currently, on different platform, the behaivor of llvm.minnum is
different if one operand is sNaN:

When we compare sNaN vs NUM:

ARM/AAr

Intrinsic: introduce minimumnum and maximumnum (#93841)

Currently, on different platform, the behaivor of llvm.minnum is
different if one operand is sNaN:

When we compare sNaN vs NUM:

ARM/AArch64/PowerPC: follow the IEEE754-2008's minNUM: return qNaN.
RISC-V/Hexagon follow the IEEE754-2019's minimumNumber: return NUM. X86:
Returns NUM but not same with IEEE754-2019's minimumNumber as
+0.0 is not always greater than -0.0.
MIPS/LoongArch/Generic: return NUM.
LIBCALL: returns qNaN.

So, let's introduce llvm.minmumnum/llvm.maximumnum, which always follow
IEEE754-2019's minimumNumber/maximumNumber.

Half-fix: #93033

show more ...

[RISCV] Avoid using x7/t2 for indirect branches which need landing pad. (#68292)

When Zicfilp enabled, this avoids selecting indirect jumps to PseudoBRIND/PseudoCALLIndirect/PseudoTAILIndirect, sinc

[RISCV] Avoid using x7/t2 for indirect branches which need landing pad. (#68292)

When Zicfilp enabled, this avoids selecting indirect jumps to PseudoBRIND/PseudoCALLIndirect/PseudoTAILIndirect, since they may uses X7 as rs1 and be identified as a software guarded jump. There is an another PR #66762 to use software guarded jump for jumptable branch.

show more ...

[X86][GISel] Add DU chain lookups for LOAD & STORE (#87453)

For G_LOAD and G_STORE we want this information during regbankselect.
Today we treat load dest as integer and insert converts.

-------

[X86][GISel] Add DU chain lookups for LOAD & STORE (#87453)

For G_LOAD and G_STORE we want this information during regbankselect.
Today we treat load dest as integer and insert converts.

---------

Co-authored-by: Evgenii Kudriashov <evgenii.kudriashov@intel.com>

show more ...

[RISCV][GISel] Make register bank selection for unary and binary arithmetic ops more generic. (#87593)

This is inspired by AArch64's getSameKindOfOperandsMapping, but based on
what RISC-V currently

[RISCV][GISel] Make register bank selection for unary and binary arithmetic ops more generic. (#87593)

This is inspired by AArch64's getSameKindOfOperandsMapping, but based on
what RISC-V currently needs.

This removes the special vector case for G_ADD/SUB and unifies integer
and FP operations into the same handler.

G_SEXTLOAD/ZEXTLOAD have been separated from integer since they should
only be scalar integer and never vector.

show more ...

[RISCV][GISel] Don't check for FP uses of of IMPLICIT_DEF if the type is vector. NFC

If the type is vector, we can immediately know to use vector mapping.
Previously we searched for FP uses, but the

[RISCV][GISel] Don't check for FP uses of of IMPLICIT_DEF if the type is vector. NFC

If the type is vector, we can immediately know to use vector mapping.
Previously we searched for FP uses, but then replaced it if the type
was vector.

show more ...

[RISCV] Remove G_TRUNC/ZEXT/SEXT/ANYEXT from the first switch in RISCVRegisterBankInfo::getInstrMapping.

This removes the special case for vectors. The default case in the
second switch can handle G

[RISCV] Remove G_TRUNC/ZEXT/SEXT/ANYEXT from the first switch in RISCVRegisterBankInfo::getInstrMapping.

This removes the special case for vectors. The default case in the
second switch can handle GPR in addition to vectors. We just won't
use the static ValueMapping entry.

show more ...

[RISCV][GISEL] Regbankselect for G_ZEXT, G_SEXT, and G_ANYEXT with scalable vector type

[RISCV][GISEL] Regbank select for scalable vector G_ICMP

[RISCV][GISEL] Regbank select for scalable G_SELECT

[RISCV][GISEL] Legalize and regbankselect vector typed G_IMPLICIT_DEF

[RISCV][GISel] RegBank select and instruction select for vector G_ADD, G_SUB (#74114)

RegisterBank Selection for scalable vector G_ADD and G_SUB by creating
new mappings for different types of vect

[RISCV][GISel] RegBank select and instruction select for vector G_ADD, G_SUB (#74114)

RegisterBank Selection for scalable vector G_ADD and G_SUB by creating
new mappings for different types of vector register banks.
Then implement Instruction Selection for the same operations by choosing
the correct RISC-V vector register class.

show more ...

[RISCV][GISEL] legalize, regbankselect, and instruction-select for G_… (#73061)

…[UN]MERGE_VALUES

When MERGE or UNMERGE s64 on a subtarget that is non-64bit, it must have
the D extension and use

[RISCV][GISEL] legalize, regbankselect, and instruction-select for G_… (#73061)

…[UN]MERGE_VALUES

When MERGE or UNMERGE s64 on a subtarget that is non-64bit, it must have
the D extension and use FPR in order to be legal.

All other instances of MERGE and UNMERGE that can be made legal should
be narrowed, widend, or replaced by the combiner.

show more ...

[RISCV][GISEL] regbankselect and instruction-select for G_IMPLICIT_DEF (#73060)

This is similar to the selection of G_IMPLICIT_DEF in AArch64.
Regbankselect may need to be improved in a future patc

[RISCV][GISEL] regbankselect and instruction-select for G_IMPLICIT_DEF (#73060)

This is similar to the selection of G_IMPLICIT_DEF in AArch64.
Regbankselect may need to be improved in a future patch.

show more ...

[RISCV][GISel] Support s64 G_SELECT on RV32 with D extension.

We have to force the register bank to FPRB if the type is s64 and
the GPR is 32 bits.

[RISCV][GISel] Support G_FCOPYSIGN with F and D extension.

[RISCV] Add register bank and instruction selection support for FP G_SELECT. (#72726)

Try to pick the FP register bank based on surrounding use/defs. Code is
basically copied from AArch64.

Need

[RISCV] Add register bank and instruction selection support for FP G_SELECT. (#72726)

Try to pick the FP register bank based on surrounding use/defs. Code is
basically copied from AArch64.

Need legalizer changes to make this more useful. Right now we're stuck
with only being able to FP select types less than or equal to XLen.

show more ...