Initialize boolean variables in MipsSubtarget's constructor.

llvm-svn: 164642

Add register Mips::GP to the list of reserved registers if target is bare-metal
to prevent it from being clobbered. mips uses $gp to access small data section.

This bug was originally reported by Ca

Add register Mips::GP to the list of reserved registers if target is bare-metal
to prevent it from being clobbered. mips uses $gp to access small data section.

This bug was originally reported by Carl Norum.

llvm-svn: 162340

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Fix coding style violations. Remove white spaces and tabs.

llvm-svn: 158471

This patch adds the register class for MIPS16 as well as the ability for
llc to recognize MIPS16 as a MIPS ASE extension. -mips16 will mean the
mips16 ASE for mips32 by default.

As part of fixing of

This patch adds the register class for MIPS16 as well as the ability for
llc to recognize MIPS16 as a MIPS ASE extension. -mips16 will mean the
mips16 ASE for mips32 by default.

As part of fixing of adding this we discovered some small changes that
need to be made to MipsInstrInfo::storeRegToStackSLot and
MipsInstrInfo::loadRegFromStackSlot. We were using some "==" equality tests
where in fact we should have been using Mips::<regclas>.hasSubClassEQ instead,
per suggestion of Jakob Stoklund Olesen.

Patch by Reed Kotler.

llvm-svn: 156958

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Temporarily disable anti-dependence breaking for Mips until bug 12829 is
resolved.

llvm-svn: 156801

Turn off post-RA scheduler by default.

llvm-svn: 153557

Turn on post register allocation scheduler.

llvm-svn: 153554

remove blanks, and some code format

llvm-svn: 151625

remove Emacs-tag form .cpp files in Mips Backend, and fix some typo.

llvm-svn: 150805

Unweaken vtables as per http://llvm.org/docs/CodingStandards.html#ll_virtual_anch

llvm-svn: 146960

Change names for MIPS "generic" processors defined in Mips.td to match what GNU
tools use. Patch by Simon Atanasyan.

"mips32r1" => "mips32"
"4ke" => mips32r2"
"mips64r1" => "mips64"

llvm-svn: 145451

Undo a change made in r140254.
MipsArchVersion needs to be initialized to Mips32.

llvm-svn: 140261

MipsArchVersion does not need to be in the initialization list and MipsABI
should be initialized to UnknownABI.

llvm-svn: 140254

Set ABI if it hasn't been set on the command line.
Check if architecture & ABI combination is valid.

llvm-svn: 140230

Drop support for Mips1 and Mips2.

llvm-svn: 139405

Drop support for Allegrex. Allegrex implements a variant of Mips2.

llvm-svn: 139383

Change default target architecture from Mips1 to Mips32r1 in preparation for
removing support for Mips1 and Mips2.

This change and the ones that follow have been discussed with and approved by
Brun

Change default target architecture from Mips1 to Mips32r1 in preparation for
removing support for Mips1 and Mips2.

This change and the ones that follow have been discussed with and approved by
Bruno.

llvm-svn: 139344

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Move TargetRegistry and TargetSelect from Target to Support where they belong.
These are strictly utilities for registering targets and components.

llvm-svn: 138450

Next round of MC refactoring. This patch factor MC table instantiations, MC
registeration and creation code into XXXMCDesc libraries.

llvm-svn: 135184

- Eliminate MCCodeEmitter's dependency on TargetMachine. It now uses MCInstrInfo
and MCSubtargetInfo.
- Added methods to update subtarget features (used when targets automatically
detect subtarge

- Eliminate MCCodeEmitter's dependency on TargetMachine. It now uses MCInstrInfo
and MCSubtargetInfo.
- Added methods to update subtarget features (used when targets automatically
detect subtarget features or switch modes).
- Teach X86Subtarget to update MCSubtargetInfo features bits since the
MCSubtargetInfo layer can be shared with other modules.
- These fixes .code 16 / .code 32 support since mode switch is updated in
MCSubtargetInfo so MC code emitter can do the right thing.

llvm-svn: 134884

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Change createAsmParser to take a MCSubtargetInfo instead of triple,
CPU, and feature string. Parsing some asm directives can change
subtarget state (e.g. .code 16) and it must be reflected in other
m

Change createAsmParser to take a MCSubtargetInfo instead of triple,
CPU, and feature string. Parsing some asm directives can change
subtarget state (e.g. .code 16) and it must be reflected in other
modules (e.g. MCCodeEmitter). That is, the MCSubtargetInfo instance
must be shared.

llvm-svn: 134795

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Eliminate asm parser's dependency on TargetMachine:
- Each target asm parser now creates its own MCSubtatgetInfo (if needed).
- Changed AssemblerPredicate to take subtarget features which tablegen us

Eliminate asm parser's dependency on TargetMachine:
- Each target asm parser now creates its own MCSubtatgetInfo (if needed).
- Changed AssemblerPredicate to take subtarget features which tablegen uses
to generate asm matcher subtarget feature queries. e.g.
"ModeThumb,FeatureThumb2" is translated to
"(Bits & ModeThumb) != 0 && (Bits & FeatureThumb2) != 0".

llvm-svn: 134678

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Compute feature bits at time of MCSubtargetInfo initialization.

llvm-svn: 134606

Rename XXXGenSubtarget.inc to XXXGenSubtargetInfo.inc for consistency.

llvm-svn: 134281

Rename TargetSubtarget to TargetSubtargetInfo for consistency.

llvm-svn: 134259