Revision tags: llvmorg-3.8.0, llvmorg-3.8.0-rc3, llvmorg-3.8.0-rc2, llvmorg-3.8.0-rc1, llvmorg-3.7.1, llvmorg-3.7.1-rc2, llvmorg-3.7.1-rc1 |
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43dff0c0 |
| 26-Oct-2015 |
Vasileios Kalintiris <Vasileios.Kalintiris@imgtec.com> |
[mips] Interrupt attribute support for mips32r2+.
Summary: This patch adds support for using the "interrupt" attribute on Mips for interrupt handling functions. At this time only mips32r2+ with the
[mips] Interrupt attribute support for mips32r2+.
Summary: This patch adds support for using the "interrupt" attribute on Mips for interrupt handling functions. At this time only mips32r2+ with the o32 ABI with the static relocation model is supported. Unsupported configurations will be rejected
Patch by Simon Dardis (+ clang-format & some trivial changes to follow the LLVM coding standards by me).
Reviewers: mpf, dsanders
Subscribers: dsanders, vkalintiris, llvm-commits
Differential Revision: http://reviews.llvm.org/D10768
llvm-svn: 251286
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Revision tags: llvmorg-3.7.0, llvmorg-3.7.0-rc4, llvmorg-3.7.0-rc3, studio-1.4 |
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5659a2f9 |
| 11-Aug-2015 |
Alex Lorenz <arphaman@gmail.com> |
PseudoSourceValue: Transform the mips subclass to target independent subclasses
This commit transforms the mips-specific 'MipsCallEntry' subclass of the 'PseudoSourceValue' class into two, target-in
PseudoSourceValue: Transform the mips subclass to target independent subclasses
This commit transforms the mips-specific 'MipsCallEntry' subclass of the 'PseudoSourceValue' class into two, target-independent subclasses named 'GlobalValuePseudoSourceValue' and 'ExternalSymbolPseudoSourceValue'.
This change makes it easier to serialize the pseudo source values by removing target-specific pseudo source values.
Reviewers: Akira Hatanaka llvm-svn: 244698
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c49e4fe9 |
| 11-Aug-2015 |
Alex Lorenz <arphaman@gmail.com> |
PseudoSourceValue: Introduce a 'PSVKind' enumerator.
This commit introduces a new enumerator named 'PSVKind' in the 'PseudoSourceValue' class. This enumerator is now used to distinguish between the
PseudoSourceValue: Introduce a 'PSVKind' enumerator.
This commit introduces a new enumerator named 'PSVKind' in the 'PseudoSourceValue' class. This enumerator is now used to distinguish between the various kinds of pseudo source values.
This change is done in preparation for the changes to the pseudo source value object management and to the PseudoSourceValue's class hierarchy - the next two PseudoSourceValue commits will get rid of the global variable that manages the pseudo source values and the mips specific MipsCallEntry subclass.
Reviewers: Akira Hatanaka llvm-svn: 244687
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Revision tags: llvmorg-3.7.0-rc2, llvmorg-3.7.0-rc1, llvmorg-3.6.2, llvmorg-3.6.2-rc1, llvmorg-3.6.1, llvmorg-3.6.1-rc1 |
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727b5051 |
| 16-Apr-2015 |
Benjamin Kramer <benny.kra@googlemail.com> |
[Mips] Use unique_ptr to manage ownership.
Required some tweaking of ValueMap to accommodate a move-only value type. No functional change intended.
llvm-svn: 235091
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Revision tags: llvmorg-3.5.2, llvmorg-3.5.2-rc1 |
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71a33e2a |
| 27-Feb-2015 |
Zoran Jovanovic <zoran.jovanovic@imgtec.com> |
[mips][microMIPS] Change register class for GP register Differential Revision: http://reviews.llvm.org/D7934
llvm-svn: 230760
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Revision tags: llvmorg-3.6.0, llvmorg-3.6.0-rc4 |
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71f308ad |
| 13-Feb-2015 |
Chandler Carruth <chandlerc@gmail.com> |
Re-sort #include lines using my handy dandy ./utils/sort_includes.py script. This is in preparation for changes to lots of include lines.
llvm-svn: 229088
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Revision tags: llvmorg-3.6.0-rc3, llvmorg-3.6.0-rc2 |
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96e72c6a |
| 29-Jan-2015 |
Eric Christopher <echristo@gmail.com> |
Remove most of the TargetMachine::getSubtarget/getSubtargetImpl calls that don't take a Function argument from Mips. Notable exceptions: the AsmPrinter and MipsTargetObjectFile. The latter needs to b
Remove most of the TargetMachine::getSubtarget/getSubtargetImpl calls that don't take a Function argument from Mips. Notable exceptions: the AsmPrinter and MipsTargetObjectFile. The latter needs to be fixed, and the former will be fixed when the general AsmPrinter changes happen.
llvm-svn: 227512
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Revision tags: llvmorg-3.6.0-rc1, llvmorg-3.5.1, llvmorg-3.5.1-rc2, llvmorg-3.5.1-rc1 |
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61e88f44 |
| 21-Nov-2014 |
Craig Topper <craig.topper@gmail.com> |
Remove a bunch of unnecessary typecasts to 'const TargetRegisterClass *'
llvm-svn: 222509
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Revision tags: llvmorg-3.5.0 |
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6dc4a8bc |
| 30-Aug-2014 |
Craig Topper <craig.topper@gmail.com> |
Fix some cases where StringRef was being passed by const reference. Remove const from some other StringRefs since its implicitly const already.
llvm-svn: 216820
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Revision tags: llvmorg-3.5.0-rc4, llvmorg-3.5.0-rc3, llvmorg-3.5.0-rc2, llvmorg-3.5.0-rc1 |
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7ddb0ab8 |
| 14-Jul-2014 |
Daniel Sanders <daniel.sanders@imgtec.com> |
[mips] For the FP64A ABI, odd-numbered double-precision moves must not use mtc1/mfc1.
Summary: This is because the FP64A the hardware will redirect 32-bit reads/writes from/to odd-numbered registers
[mips] For the FP64A ABI, odd-numbered double-precision moves must not use mtc1/mfc1.
Summary: This is because the FP64A the hardware will redirect 32-bit reads/writes from/to odd-numbered registers to the upper 32-bits of the corresponding even register. In effect, simulating FR=0 mode when FR=0 mode is not available.
Unfortunately, we have to make the decision to avoid mfc1/mtc1 before register allocation so we currently do this for even registers too.
FPXX has a similar requirement on 32-bit architectures that lack mfhc1/mthc1 so this patch also handles the affected moves from the FPU for FPXX too. Moves to the FPU were supported by an earlier commit.
Differential Revision: http://reviews.llvm.org/D4484
llvm-svn: 212938
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b976fee8 |
| 14-Jul-2014 |
Sasa Stankovic <Sasa.Stankovic@imgtec.com> |
[mips] Expand BuildPairF64 to a spill and reload when the O32 FPXX ABI is enabled and mthc1 and dmtc1 are not available (e.g. on MIPS32r1)
This prevents the upper 32-bits of a double precision value
[mips] Expand BuildPairF64 to a spill and reload when the O32 FPXX ABI is enabled and mthc1 and dmtc1 are not available (e.g. on MIPS32r1)
This prevents the upper 32-bits of a double precision value from being moved to the FPU with mtc1 to an odd-numbered FPU register. This is necessary to ensure that the code generated executes correctly regardless of the current FPU mode.
MIPS32r2 and above continues to use mtc1/mthc1, while MIPS-IV and above continue to use dmtc1.
Differential Revision: http://reviews.llvm.org/D4465
llvm-svn: 212930
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Revision tags: llvmorg-3.4.2, llvmorg-3.4.2-rc1 |
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de3e36be |
| 07-May-2014 |
Rafael Espindola <rafael.espindola@gmail.com> |
Use range loop.
llvm-svn: 208218
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e73658dd |
| 28-Apr-2014 |
Craig Topper <craig.topper@gmail.com> |
[C++] Use 'nullptr'.
llvm-svn: 207394
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Revision tags: llvmorg-3.4.1, llvmorg-3.4.1-rc2, llvmorg-3.4.1-rc1, llvmorg-3.4.0, llvmorg-3.4.0-rc3, llvmorg-3.4.0-rc2, llvmorg-3.4.0-rc1 |
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ee909cc2 |
| 08-Oct-2013 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] Simplify and optimize code.
No intended functionality change.
llvm-svn: 192213
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3fddccfa |
| 28-Sep-2013 |
NAKAMURA Takumi <geek4civic@gmail.com> |
MipsMachineFunction.cpp: Add missing #include <raw_ostream.h>
llvm-svn: 191597
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e0657b24 |
| 27-Sep-2013 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] Define a derived class of PseudoSourceValue that represents a GOT entry resolved by lazy-binding.
llvm-svn: 191578
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13e6ccf3 |
| 06-Aug-2013 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] Rename register classes CPURegs and CPU64Regs.
llvm-svn: 187832
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Revision tags: llvmorg-3.3.1-rc1, llvmorg-3.3.0, llvmorg-3.3.0-rc3, llvmorg-3.3.0-rc2, llvmorg-3.3.0-rc1 |
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c0b02069 |
| 30-Jan-2013 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] Lower EH_RETURN.
Patch by Sasa Stankovic.
llvm-svn: 173862
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9fb823bb |
| 02-Jan-2013 |
Chandler Carruth <chandlerc@gmail.com> |
Move all of the header files which are involved in modelling the LLVM IR into their new header subdirectory: include/llvm/IR. This matches the directory structure of lib, and begins to correct a long
Move all of the header files which are involved in modelling the LLVM IR into their new header subdirectory: include/llvm/IR. This matches the directory structure of lib, and begins to correct a long standing point of file layout clutter in LLVM.
There are still more header files to move here, but I wanted to handle them in separate commits to make tracking what files make sense at each layer easier.
The only really questionable files here are the target intrinsic tablegen files. But that's a battle I'd rather not fight today.
I've updated both CMake and Makefile build systems (I think, and my tests think, but I may have missed something).
I've also re-sorted the includes throughout the project. I'll be committing updates to Clang, DragonEgg, and Polly momentarily.
llvm-svn: 171366
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Revision tags: llvmorg-3.2.0, llvmorg-3.2.0-rc3 |
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ed0881b2 |
| 03-Dec-2012 |
Chandler Carruth <chandlerc@gmail.com> |
Use the new script to sort the includes of every file under lib.
Sooooo many of these had incorrect or strange main module includes. I have manually inspected all of these, and fixed the main module
Use the new script to sort the includes of every file under lib.
Sooooo many of these had incorrect or strange main module includes. I have manually inspected all of these, and fixed the main module include to be the nearest plausible thing I could find. If you own or care about any of these source files, I encourage you to take some time and check that these edits were sensible. I can't have broken anything (I strictly added headers, and reordered them, never removed), but they may not be the headers you'd really like to identify as containing the API being implemented.
Many forward declarations and missing includes were added to a header files to allow them to parse cleanly when included first. The main module rule does in fact have its merits. =]
llvm-svn: 169131
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Revision tags: llvmorg-3.2.0-rc2, llvmorg-3.2.0-rc1 |
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3589dd74 |
| 28-Oct-2012 |
Reed Kotler <rkotler@mips.com> |
This patch is for the implementation of mips16 complex pattern addr16. Previously mips16 was sharing the pattern addr which is used for mips32 and mips64. This had a number of problems: 1) Storing an
This patch is for the implementation of mips16 complex pattern addr16. Previously mips16 was sharing the pattern addr which is used for mips32 and mips64. This had a number of problems: 1) Storing and loading byte and halfword quantities for mips16 has particular problems due to the primarily non mips16 nature of SP. When we must load/store byte/halfword stack objects in a function, we must create a mips16 alias register for SP. This functionality is tested in stchar.ll. 2) We need to have an FP register under certain conditions (such as dynamically sized alloca). We use mips16 register S0 for this purpose. In this case, we also use this register when accessing frame objects so this issue also affects the complex pattern addr16. This functionality is tested in alloca16.ll.
The Mips16InstrInfo.td has been updated to use addr16 instead of addr.
The complex pattern C++ function for addr has been copied to addr16 and updated to reflect the above issues.
llvm-svn: 166897
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26e9ecb7 |
| 23-Jul-2012 |
Akira Hatanaka <ahatanaka@mips.com> |
Add basic ability to setup call frame, and make procedure calls. Hello world will compile and execute with this patch.
Patch by Reed Kotler.
llvm-svn: 160651
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b49c68a6 |
| 21-Jul-2012 |
Akira Hatanaka <ahatanaka@mips.com> |
Revert accidental commit.
llvm-svn: 160598
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f73e3627 |
| 21-Jul-2012 |
Akira Hatanaka <ahatanaka@mips.com> |
Add VK_Mips_HIGHER and VK_Mips_HIGHEST to MCSymbolRefExpr::VariantKind.
Test case will be added later when long branch patch is checked in.
llvm-svn: 160597
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Revision tags: llvmorg-3.1.0 |
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3ecc5273 |
| 12-May-2012 |
Akira Hatanaka <ahatanaka@mips.com> |
Delete all functions that are no longer needed in MipsFunctionInfo, including the ones that get or set the frame index for the $gp save slot.
Remove the piece of code in MipsFunctionInfo::getGlobal
Delete all functions that are no longer needed in MipsFunctionInfo, including the ones that get or set the frame index for the $gp save slot.
Remove the piece of code in MipsFunctionInfo::getGlobalBaseReg() which returns GP. This function should always return a virtual register.
llvm-svn: 156695
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