[mips][microMIPS] Implement ADDU16, AND16, ANDI16, NOT16, OR16, SLL16 and SRL16 instructions
Differential Revision: http://reviews.llvm.org/D11178

llvm-svn: 247146

[mips][microMIPS] Implement CACHEE and PREFE instructions
Differential Revision: http://reviews.llvm.org/D11628

llvm-svn: 247125

[mips][microMIPS] Implement SB, SBE, SCE, SH and SHE instructions
Differential Revision: http://reviews.llvm.org/D11801

llvm-svn: 246999

[mips][microMIPS] Implement BC16, BEQZC16 and BNEZC16 instructions
Differential Revision: http://reviews.llvm.org/D11181

llvm-svn: 246963

[mips][microMIPS] Implement SW and SWE instructions
Differential Revision: http://reviews.llvm.org/D10869

llvm-svn: 245293

[mips][microMIPS] Create microMIPS64r6 subtarget and implement DALIGN, DAUI, DAHI, DATI, DEXT, DEXTM and DEXTU instructions
Differential Revision: http://reviews.llvm.org/D10923

llvm-svn: 244744

[mips] Add COP0 register class and use it in M[FT]C0/DM[FT]C0.

Summary:
Previously it (incorrectly) used GPR's.

Patch by Simon Dardis. A couple small corrections by myself.

Reviewers: dsanders

Re

[mips] Add COP0 register class and use it in M[FT]C0/DM[FT]C0.

Summary:
Previously it (incorrectly) used GPR's.

Patch by Simon Dardis. A couple small corrections by myself.

Reviewers: dsanders

Reviewed By: dsanders

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D10567

llvm-svn: 240883

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[mips] Fix some UB by shifting before sign-extending

Avoid shifting a negative value by sign-extending after the shift.

Fixes a couple of tests that were failing under ubsan.

llvm-svn: 240381

[mips] Add new format for dmtc2/dmfc2 for Octeon CPUs.

Octeon CPUs use dmtc2 rt,imm16 and dmfcp2 rt,imm16 for the crypto coprocessor.
E.g. dmtc2 rt,0x4057 starts calculation of sha-1.

I had to intr

[mips] Add new format for dmtc2/dmfc2 for Octeon CPUs.

Octeon CPUs use dmtc2 rt,imm16 and dmfcp2 rt,imm16 for the crypto coprocessor.
E.g. dmtc2 rt,0x4057 starts calculation of sha-1.

I had to introduce a new deconding namespace to avoid a decoding conflict.

Reviewed By: dsanders

Differential Revision: http://reviews.llvm.org/D10083

llvm-svn: 238439

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Use std::bitset for SubtargetFeatures.

Previously, subtarget features were a bitfield with the underlying type being uint64_t.
Since several targets (X86 and ARM, in particular) have hit or were ve

Use std::bitset for SubtargetFeatures.

Previously, subtarget features were a bitfield with the underlying type being uint64_t.
Since several targets (X86 and ARM, in particular) have hit or were very close to hitting this bound, switching the features to use a bitset.
No functional change.

The first several times this was committed (e.g. r229831, r233055), it caused several buildbot failures.
Apparently the reason for most failures was both clang and gcc's inability to deal with large numbers (> 10K) of bitset constructor calls in tablegen-generated initializers of instruction info tables.
This should now be fixed.

llvm-svn: 238192

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MC: Modernize MCOperand API naming. NFC.

MCOperand::Create*() methods renamed to MCOperand::create*().

llvm-svn: 237275

Reverting r237234, "Use std::bitset for SubtargetFeatures"

The buildbots are still not satisfied.
MIPS and ARM are failing (even though at least MIPS was expected to pass).

llvm-svn: 237245

Use std::bitset for SubtargetFeatures

Previously, subtarget features were a bitfield with the underlying type being uint64_t.
Since several targets (X86 and ARM, in particular) have hit or were ver

Use std::bitset for SubtargetFeatures

Previously, subtarget features were a bitfield with the underlying type being uint64_t.
Since several targets (X86 and ARM, in particular) have hit or were very close to hitting this bound, switching the features to use a bitset.
No functional change.

The first two times this was committed (r229831, r233055), it caused several buildbot failures.
At least some of the ARM and MIPS ones were due to gcc/binutils issues, and should now be fixed.

llvm-svn: 237234

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[mips][microMIPSr6] Implement disassembler support

Implement disassembler support for microMIPS32r6.

Differential Revision: http://reviews.llvm.org/D8490

llvm-svn: 235307

Revert "Use std::bitset for SubtargetFeatures"

This reverts commit r233055.

It still causes buildbot failures (gcc running out of memory on several platforms, and a self-host failure on arm), altho

Revert "Use std::bitset for SubtargetFeatures"

This reverts commit r233055.

It still causes buildbot failures (gcc running out of memory on several platforms, and a self-host failure on arm), although less than the previous time.

llvm-svn: 233068

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Use std::bitset for SubtargetFeatures

Previously, subtarget features were a bitfield with the underlying type being uint64_t.
Since several targets (X86 and ARM, in particular) have hit or were ver

Use std::bitset for SubtargetFeatures

Previously, subtarget features were a bitfield with the underlying type being uint64_t.
Since several targets (X86 and ARM, in particular) have hit or were very close to hitting this bound, switching the features to use a bitset.
No functional change.

The first time this was committed (r229831), it caused several buildbot failures.
At least some of the ARM ones were due to gcc/binutils issues, and should now be fixed.

Differential Revision: http://reviews.llvm.org/D8542

llvm-svn: 233055

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Reverting r229831 due to multiple ARM/PPC/MIPS build-bot failures.

llvm-svn: 229841

Use std::bitset for SubtargetFeatures

Previously, subtarget features were a bitfield with the underlying type being uint64_t.
Since several targets (X86 and ARM, in particular) have hit or were ver

Use std::bitset for SubtargetFeatures

Previously, subtarget features were a bitfield with the underlying type being uint64_t.
Since several targets (X86 and ARM, in particular) have hit or were very close to hitting this bound, switching the features to use a bitset.

No functional change.

Differential Revision: http://reviews.llvm.org/D7065

llvm-svn: 229831

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[mips] Merge disassemblers into a single implementation.

Summary:
Currently we have Mips32 and Mips64 disassemblers and this causes the target
triple to affect the disassembly despite all the releva

[mips] Merge disassemblers into a single implementation.

Summary:
Currently we have Mips32 and Mips64 disassemblers and this causes the target
triple to affect the disassembly despite all the relevant information being in
the ELF header. These implementations do not need to be separate.

This patch merges them together such that the appropriate tables are checked
for the subtarget (e.g. Mips64 is checked when GP64 is enabled).

Reviewers: vmedic

Reviewed By: vmedic

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D7498

llvm-svn: 228825

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[mips][microMIPS] Implement movep instruction
Differential Revision: http://reviews.llvm.org/D7465

llvm-svn: 228703

[mips][microMIPS] Fix disassembling of 16-bit microMIPS instructions LWM16 and SWM16

Differential Revision: http://reviews.llvm.org/D7436

llvm-svn: 228683

[Mips][Disassembler] When disassembler meets cache/pref instructions for r6 it crashes as the access to operands array is out of range. This patch adds dedicated decoder method for R6 CACHE_HINT_DESC

[Mips][Disassembler] When disassembler meets cache/pref instructions for r6 it crashes as the access to operands array is out of range. This patch adds dedicated decoder method for R6 CACHE_HINT_DESC class that properly handles decoding of these instructions.

llvm-svn: 227430

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[mips][microMIPS] Implement LWGP instruction

Differential Revision: http://reviews.llvm.org/D6650

llvm-svn: 227325

[mips] fix spelling of 'disassembler'

trivial first commit

llvm-svn: 226935

[mips][microMIPS] MicroMIPS 16-bit unconditional branch instruction B

Implement microMIPS 16-bit unconditional branch instruction B.

Implemented 16-bit microMIPS unconditional instruction has real

[mips][microMIPS] MicroMIPS 16-bit unconditional branch instruction B

Implement microMIPS 16-bit unconditional branch instruction B.

Implemented 16-bit microMIPS unconditional instruction has real name B16, and
B is an alias which expands to either B16 or BEQ according to the rules:
b 256 --> b16 256 # R_MICROMIPS_PC10_S1
b 12256 --> beq $zero, $zero, 12256 # R_MICROMIPS_PC16_S1
b label --> beq $zero, $zero, label # R_MICROMIPS_PC16_S1

Differential Revision: http://reviews.llvm.org/D3514

llvm-svn: 226657

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