This patch adds support for microMIPS disassembler and disassembler make check tests.

llvm-svn: 190144

[mips] Use ptr_rc to simplify definitions of base+index load/store instructions.
Also, fix predicates.

llvm-svn: 189432

[mips] Define register class FGRH32 for the high half of the 64-bit floating
point registers. We will need this register class later when we add
definitions for instructions mfhc1 and mthc1. Also, re

[mips] Define register class FGRH32 for the high half of the 64-bit floating
point registers. We will need this register class later when we add
definitions for instructions mfhc1 and mthc1. Also, remove sub-register indices
sub_fpeven and sub_fpodd and use sub_lo and sub_hi instead.

llvm-svn: 188842

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[mips] Rename DSPRegs.

llvm-svn: 188342

[mips] Rename HIRegs and LORegs.

llvm-svn: 188341

[mips] Rename accumulator register classes and FP register operands.

llvm-svn: 188020

Remove unused functions introduced in r172685 to unbreak the Clang -Werror build

llvm-svn: 187838

[mips] Rename register classes CPURegs and CPU64Regs.

llvm-svn: 187832

Stop leaking register infos in the disassemblers.

llvm-svn: 187695

[mips] Fix FP branch instructions to have explicit FP condition code register
operands.

llvm-svn: 187238

Fixing a buildbot failure:unused function.

llvm-svn: 186403

[Mips Disassembler] Have the DecodeCCRRegisterClass function use the getReg
function to lookup the proper tablegen'ed register enumeration. Previously,
it was using the encoded value directly.

llvm

[Mips Disassembler] Have the DecodeCCRRegisterClass function use the getReg
function to lookup the proper tablegen'ed register enumeration. Previously,
it was using the encoded value directly.

llvm-svn: 185026

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Remove the Copied parameter from MemoryObject::readBytes.

There was exactly one caller using this API right, the others were relying on
specific behavior of the default implementation. Since it's to

Remove the Copied parameter from MemoryObject::readBytes.

There was exactly one caller using this API right, the others were relying on
specific behavior of the default implementation. Since it's too hard to use it
right just remove it and standardize on the default behavior.

Defines away PR16132.

llvm-svn: 182636

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[mips] DSP-ASE move from HI/LO register instructions.

llvm-svn: 179739

[mips] Fix DSP instructions to have explicit accumulator register operands.

Check that instruction selection can select multiply-add/sub DSP instructions
from a pattern that doesn't have intrinsics.

[mips] Fix DSP instructions to have explicit accumulator register operands.

Check that instruction selection can select multiply-add/sub DSP instructions
from a pattern that doesn't have intrinsics.

llvm-svn: 178406

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Remove the form field from Mips16 instruction formats and set things
up so that we can apply the direct object emitter patch. This patch
should be a nop right now and it's test is to not break what i

Remove the form field from Mips16 instruction formats and set things
up so that we can apply the direct object emitter patch. This patch
should be a nop right now and it's test is to not break what is already
there.


llvm-svn: 175126

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This is a resubmittal. For some reason it broke the bots yesterday
but I cannot reproduce the problem and have scrubed my sources and
even tested with llvm-lit -v --vg.

The Mips RDHWR (Read Hardware

This is a resubmittal. For some reason it broke the bots yesterday
but I cannot reproduce the problem and have scrubed my sources and
even tested with llvm-lit -v --vg.

The Mips RDHWR (Read Hardware Register) instruction was not
tested for assembler or dissassembler consumption. This patch
adds that functionality.

Contributer: Vladimir Medic

llvm-svn: 172685

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reverting 172579

llvm-svn: 172594

Akira,

Hope you are feeling better.

The Mips RDHWR (Read Hardware Register) instruction was not
tested for assembler or dissassembler consumption. This patch
adds that functionality.

Contributer:

Akira,

Hope you are feeling better.

The Mips RDHWR (Read Hardware Register) instruction was not
tested for assembler or dissassembler consumption. This patch
adds that functionality.

Contributer: Vladimir Medic

llvm-svn: 172579

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MipsDisassembler.cpp: Prune DecodeHWRegs64RegisterClass() to suppress a warning. [-Wunused-function]

llvm-svn: 172319

Remove edis - the enhanced disassembler. Fixes PR14654.

llvm-svn: 170578

Use the new script to sort the includes of every file under lib.

Sooooo many of these had incorrect or strange main module includes.
I have manually inspected all of these, and fixed the main module

Use the new script to sort the includes of every file under lib.

Sooooo many of these had incorrect or strange main module includes.
I have manually inspected all of these, and fixed the main module
include to be the nearest plausible thing I could find. If you own or
care about any of these source files, I encourage you to take some time
and check that these edits were sensible. I can't have broken anything
(I strictly added headers, and reordered them, never removed), but they
may not be the headers you'd really like to identify as containing the
API being implemented.

Many forward declarations and missing includes were added to a header
files to allow them to parse cleanly when included first. The main
module rule does in fact have its merits. =]

llvm-svn: 169131

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MIPS DSP: add functions which decode DSP and accumulator registers.

llvm-svn: 164748

Switch the fixed-length disassembler to be table-driven.

Refactor the TableGen'erated fixed length disassemblmer to use a
table-driven state machine rather than a massive set of nested
switch() stat

Switch the fixed-length disassembler to be table-driven.

Refactor the TableGen'erated fixed length disassemblmer to use a
table-driven state machine rather than a massive set of nested
switch() statements.

As a result, the ARM Disassembler (ARMDisassembler.cpp) builds much more
quickly and generates a smaller end result. For a Release+Asserts build on
a 16GB 3.4GHz i7 iMac w/ SSD:

Time to compile at -O2 (averaged w/ hot caches):
Previous: 35.5s
New: 8.9s

TEXT size:
Previous: 447,251
New: 297,661

Builds in 25% of the time previously required and generates code 66% of
the size.

Execution time of the disassembler is only slightly slower (7% disassembling
10 million ARM instructions, 19.6s vs 21.0s). The new implementation has
not yet been tuned, however, so the performance should almost certainly
be recoverable should it become a concern.

llvm-svn: 161888

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Reapply r158846.

Access mips register classes via MCRegisterInfo's functions instead of via the
TargetRegisterClasses defined in MipsGenRegisterInfo.inc.

llvm-svn: 159953