[mips][microMIPS] Implement ADDIUPC instruction

Differential Revision: http://reviews.llvm.org/D6582

llvm-svn: 226656

[Mips][Disassembler]When disassembler meets load/store from coprocessor 2 instructions for mips r6 it crashes as the access to operands array is out of range. This patch adds dedicated decoder method

[Mips][Disassembler]When disassembler meets load/store from coprocessor 2 instructions for mips r6 it crashes as the access to operands array is out of range. This patch adds dedicated decoder method that properly handles decoding of these instructions.

llvm-svn: 226652

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Reverted revision 226577.

llvm-svn: 226595

[mips][microMIPS] MicroMIPS 16-bit unconditional branch instruction B

Implement microMIPS 16-bit unconditional branch instruction B.

Implemented 16-bit microMIPS unconditional instruction has real

[mips][microMIPS] MicroMIPS 16-bit unconditional branch instruction B

Implement microMIPS 16-bit unconditional branch instruction B.

Implemented 16-bit microMIPS unconditional instruction has real name B16, and
B is an alias which expands to either B16 or BEQ according to the rules:
b 256 --> b16 256 # R_MICROMIPS_PC10_S1
b 12256 --> beq $zero, $zero, 12256 # R_MICROMIPS_PC16_S1
b label --> beq $zero, $zero, label # R_MICROMIPS_PC16_S1

Differential Revision: http://reviews.llvm.org/D3514

llvm-svn: 226577

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[mips][microMIPS] Implement BEQZ16 and BNEZ16 instructions

Differential Revision: http://reviews.llvm.org/D5271

llvm-svn: 225627

[mips][microMIPS] Implement CACHE, PREF, SSNOP, EHB and PAUSE instructions

Differential Revision: http://reviews.llvm.org/D5204

llvm-svn: 224785

[mips][microMIPS] Implement LWSP and SWSP instructions

Differential Revision: http://reviews.llvm.org/D6416

llvm-svn: 224771

Fix UBSan bootstrap: replace shift of negative value with multiplication.

llvm-svn: 224752

The single check for N64 inside MipsDisassemblerBase's subclasses is actually wrong. It should be testing for FeatureGP64bit.There are no functional changes.

llvm-svn: 224339

[mips][microMIPS] Implement SWP and LWP instructions
Differential Revision: http://reviews.llvm.org/D5667

llvm-svn: 224338

Add disassembler tests for mips3 platform. There are no functional changes.

llvm-svn: 224253

The andi16, addiusp and jraddiusp micromips instructions were missing dedicated decoder methods in MipsDisassembler.cpp to properly decode immediate operands. These methods are added together with co

The andi16, addiusp and jraddiusp micromips instructions were missing dedicated decoder methods in MipsDisassembler.cpp to properly decode immediate operands. These methods are added together with corresponding tests.

llvm-svn: 223006

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[mips][microMIPS] Implement SWM16 and LWM16 instructions
Differential Revision: http://reviews.llvm.org/D5579

llvm-svn: 222901

[mips] Add synci instruction.

Patch by Amaury Pouly

Reviewers: dsanders

Reviewed By: dsanders

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D6421

llvm-svn: 222899

[mips][microMIPS] Implement disassembler support for 16-bit instructions LI16, ADDIUR1SP, ADDIUR2 and ADDIUS5

Differential Revision: http://reviews.llvm.org/D6419

llvm-svn: 222887

[mips][microMIPS] Implement disassembler support for 16-bit instructions LBU16, LHU16, LW16, SB16, SH16 and SW16

Differential Revision: http://reviews.llvm.org/D6405

llvm-svn: 222847

[mips][microMIPS] Implement 16-bit instructions registers including ZERO instead of S0

Implement microMIPS 16-bit instructions register set: $0, $2-$7 and $17.

Differential Revision: http://reviews

[mips][microMIPS] Implement 16-bit instructions registers including ZERO instead of S0

Implement microMIPS 16-bit instructions register set: $0, $2-$7 and $17.

Differential Revision: http://reviews.llvm.org/D5780

llvm-svn: 222652

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[mips][microMIPS] Implement disassembler support for 16-bit instructions

With the help of new method readInstruction16() two bytes are read and
decodeInstruction() is called with DecoderTableMicroMi

[mips][microMIPS] Implement disassembler support for 16-bit instructions

With the help of new method readInstruction16() two bytes are read and
decodeInstruction() is called with DecoderTableMicroMips16, if this fails
four bytes are read and decodeInstruction() is called with
DecoderTableMicroMips32.

Differential Revision: http://reviews.llvm.org/D6149

llvm-svn: 222648

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[mips][micromips] Implement SWM32 and LWM32 instructions
Differential Revision: http://reviews.llvm.org/D5519

llvm-svn: 222367

Pass an ArrayRef to MCDisassembler::getInstruction.

With this patch MCDisassembler::getInstruction takes an ArrayRef<uint8_t>
instead of a MemoryObject.

Even on X86 there is a maximum size an instr

Pass an ArrayRef to MCDisassembler::getInstruction.

With this patch MCDisassembler::getInstruction takes an ArrayRef<uint8_t>
instead of a MemoryObject.

Even on X86 there is a maximum size an instruction can have. Given
that, it seems way simpler and more efficient to just pass an ArrayRef
to the disassembler instead of a MemoryObject and have it do a virtual
call every time it wants some extra bytes.

llvm-svn: 221751

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Misc style fixes. NFC.

This fixes a few cases of:

* Wrong variable name style.
* Lines longer than 80 columns.
* Repeated names in comments.
* clang-format of the above.

This make the next patch a

Misc style fixes. NFC.

This fixes a few cases of:

* Wrong variable name style.
* Lines longer than 80 columns.
* Repeated names in comments.
* clang-format of the above.

This make the next patch a lot easier to read.

llvm-svn: 221615

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[mips][microMIPS] Implement microMIPS 16-bit instructions registers
Differential Revision: http://reviews.llvm.org/D5116

llvm-svn: 220273

[mips] Fix disassembly of [ls][wd]c[23], cache, and pref

Fixes PR21015, and PR20993.

[mips] Fix disassembly of [ls][wd]c[23], cache, and pref

Fixes PR21015, and PR20993.

Patch by Jun Koi

llvm-svn: 218745

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Fix left shifts of negative values in MipsDisassembler.

This bug was reported by UBSan.

llvm-svn: 216920

[mips] Use MFHC1 when it is available (MIPS32r2 and later) for both FP32 and FP64 moves

Summary:
This is similar to r210771 which did the same thing for MTHC1.

Also corrected MTHC1_D32 and MTHC1_D6

[mips] Use MFHC1 when it is available (MIPS32r2 and later) for both FP32 and FP64 moves

Summary:
This is similar to r210771 which did the same thing for MTHC1.

Also corrected MTHC1_D32 and MTHC1_D64 which used AFGR64 and FGR64 on the
wrong definitions.

Differential Revision: http://reviews.llvm.org/D4483

llvm-svn: 212936

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