Revision tags: llvmorg-5.0.0-rc1, llvmorg-4.0.1, llvmorg-4.0.1-rc3 |
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6bda14b3 |
| 06-Jun-2017 |
Chandler Carruth <chandlerc@gmail.com> |
Sort the remaining #include lines in include/... and lib/....
I did this a long time ago with a janky python script, but now clang-format has built-in support for this. I fed clang-format every line
Sort the remaining #include lines in include/... and lib/....
I did this a long time ago with a janky python script, but now clang-format has built-in support for this. I fed clang-format every line with a #include and let it re-sort things according to the precise LLVM rules for include ordering baked into clang-format these days.
I've reverted a number of files where the results of sorting includes isn't healthy. Either places where we have legacy code relying on particular include ordering (where possible, I'll fix these separately) or where we have particular formatting around #include lines that I didn't want to disturb in this patch.
This patch is *entirely* mechanical. If you get merge conflicts or anything, just ignore the changes in this patch and run clang-format over your #include lines in the files.
Sorry for any noise here, but it is important to keep these things stable. I was seeing an increasing number of patches with irrelevant re-ordering of #include lines because clang-format was used. This patch at least isolates that churn, makes it easy to skip when resolving conflicts, and gets us to a clean baseline (again).
llvm-svn: 304787
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Revision tags: llvmorg-4.0.1-rc2, llvmorg-4.0.1-rc1 |
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643aaea5 |
| 14-Apr-2017 |
Krzysztof Parzyszek <kparzysz@codeaurora.org> |
[Hexagon] Make a couple of passes compliant with -opt-bisect-limit
llvm-svn: 300329
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Revision tags: llvmorg-4.0.0, llvmorg-4.0.0-rc4, llvmorg-4.0.0-rc3 |
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1aaf41af |
| 17-Feb-2017 |
Krzysztof Parzyszek <kparzysz@codeaurora.org> |
[Hexagon] Start using regmasks on calls
Reapply r295371 with a fix for the Windows bot failures.
llvm-svn: 295504
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6eab4044 |
| 17-Feb-2017 |
Rafael Espindola <rafael.espindola@gmail.com> |
Revert "[Hexagon] Start using regmasks on calls"
This reverts commit r295371.
It broke windows bots:
http://bb.pgr.jp/builders/ninja-clang-i686-msc19-R/builds/11402/steps/test-llvm/logs/stdio
llv
Revert "[Hexagon] Start using regmasks on calls"
This reverts commit r295371.
It broke windows bots:
http://bb.pgr.jp/builders/ninja-clang-i686-msc19-R/builds/11402/steps/test-llvm/logs/stdio
llvm-svn: 295402
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fb9503c0 |
| 16-Feb-2017 |
Krzysztof Parzyszek <kparzysz@codeaurora.org> |
[Hexagon] Start using regmasks on calls
All the cool targets are doing it...
llvm-svn: 295371
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Revision tags: llvmorg-4.0.0-rc2, llvmorg-4.0.0-rc1, llvmorg-3.9.1, llvmorg-3.9.1-rc3, llvmorg-3.9.1-rc2, llvmorg-3.9.1-rc1 |
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f817efbb |
| 09-Nov-2016 |
Krzysztof Parzyszek <kparzysz@codeaurora.org> |
[Hexagon] Silence "sometimes uninitialized" warning in HexagonCopyToCombine
llvm-svn: 286383
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a540997c |
| 09-Nov-2016 |
Krzysztof Parzyszek <kparzysz@codeaurora.org> |
[Hexagon] Separate Hexagon subreg indices for different register classes
For pairs of 32-bit registers: isub_lo, isub_hi. For pairs of vector registers: vsub_lo, vsub_hi.
Add generic subreg indices
[Hexagon] Separate Hexagon subreg indices for different register classes
For pairs of 32-bit registers: isub_lo, isub_hi. For pairs of vector registers: vsub_lo, vsub_hi.
Add generic subreg indices: ps_sub_lo, ps_sub_hi, and a function HexagonRegisterInfo::getHexagonSubRegIndex(RegClass, GenericSubreg) that returns the appropriate subreg index for RegClass.
llvm-svn: 286377
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117296c0 |
| 01-Oct-2016 |
Mehdi Amini <mehdi.amini@apple.com> |
Use StringRef in Pass/PassManager APIs (NFC)
llvm-svn: 283004
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a3c739b9 |
| 25-Aug-2016 |
Ron Lieberman <ronl@codeaurora.org> |
[Hexagon] Remove extraneous debug output from HexagonCopyToCombine.cpp BB# ...
llvm-svn: 279750
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1eb47368 |
| 25-Aug-2016 |
Matthias Braun <matze@braunis.de> |
MachineFunctionProperties/MIRParser: Rename AllVRegsAllocated->NoVRegs, compute it
Rename AllVRegsAllocated to NoVRegs. This avoids the connotation of running after register and simply describes tha
MachineFunctionProperties/MIRParser: Rename AllVRegsAllocated->NoVRegs, compute it
Rename AllVRegsAllocated to NoVRegs. This avoids the connotation of running after register and simply describes that no vregs are used in a machine function. With that we can simply compute the property and do not need to dump/parse it in .mir files.
Differential Revision: http://reviews.llvm.org/D23850
llvm-svn: 279698
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Revision tags: llvmorg-3.9.0, llvmorg-3.9.0-rc3 |
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6dff336a |
| 24-Aug-2016 |
Krzysztof Parzyszek <kparzysz@codeaurora.org> |
[Hexagon] Check for block end when skipping debug instructions
llvm-svn: 279681
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Revision tags: llvmorg-3.9.0-rc2 |
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b1b03723 |
| 18-Aug-2016 |
Krzysztof Parzyszek <kparzysz@codeaurora.org> |
[Hexagon] Create vcombine in HexagonCopyToCombine
llvm-svn: 279067
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f197b1f7 |
| 12-Aug-2016 |
Duncan P. N. Exon Smith <dexonsmith@apple.com> |
ADT: Remove all ilist_iterator => pointer casts, NFC
Remove all ilist_iterator to pointer casts. There were two reasons for casts:
- Checking for an uninitialized (i.e., null) iterator. I added
ADT: Remove all ilist_iterator => pointer casts, NFC
Remove all ilist_iterator to pointer casts. There were two reasons for casts:
- Checking for an uninitialized (i.e., null) iterator. I added MachineInstrBundleIterator::isValid() to check for that case.
- Comparing an iterator against the underlying pointer value while avoiding converting the pointer value to an iterator. This is occasionally necessary in MachineInstrBundleIterator, since there is an assertion in the constructors that the underlying MachineInstr is not bundled (but we don't care about that if we're just checking for pointer equality).
To support the latter case, I rewrote the == and != operators for ilist_iterator and MachineInstrBundleIterator.
- The implicit constructors now use enable_if to exclude const-iterator => non-const-iterator conversions from overload resolution (previously it was a compiler error on instantiation, now it's SFINAE).
- The == and != operators are now global (friends), and are not templated.
- MachineInstrBundleIterator has overloads to compare against both const_pointer and const_reference. This avoids the implicit conversions to MachineInstrBundleIterator that assert, instead just checking the address (and I added unit tests to confirm this).
Notably, the only remaining uses of ilist_iterator::getNodePtrUnchecked are in ilist.h, and no code outside of ilist*.h directly relies on this UB end-iterator-to-pointer conversion anymore. It's still needed for ilist_*sentinel_traits, but I'll clean that up soon.
llvm-svn: 278478
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ec30cc21 |
| 11-Aug-2016 |
Duncan P. N. Exon Smith <dexonsmith@apple.com> |
Hexagon: Avoid dereferencing end() in HexagonCopyToCombine::findPairable
Check for end() before skipping through debug values. This avoids dereferencing end() when the instruction is the final one
Hexagon: Avoid dereferencing end() in HexagonCopyToCombine::findPairable
Check for end() before skipping through debug values. This avoids dereferencing end() when the instruction is the final one in the basic block. (It still assumes that a debug value will not be the final instruction in the basic block. No tests seemed to violate that.)
Many Hexagon tests trigger this, but they happen to magically pass right now. I found this because WIP patches for PR26753 convert them into crashes.
llvm-svn: 278355
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a3386501 |
| 10-Aug-2016 |
Krzysztof Parzyszek <kparzysz@codeaurora.org> |
[Hexagon] Use integer instructions for floating point immediates
Floating point instructions use general purpose registers, so the few instructions that can put floating point immediates into regist
[Hexagon] Use integer instructions for floating point immediates
Floating point instructions use general purpose registers, so the few instructions that can put floating point immediates into registers are, in fact, integer instruction. Use them explicitly instead of having pseudo-instructions specifically for dealing with floating point values.
Simplify the constant loading instructions (from sdata) to have only two: one for 32-bit values and one for 64-bit values: CONST32 and CONST64.
llvm-svn: 278244
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f0b34a5c |
| 29-Jul-2016 |
Krzysztof Parzyszek <kparzysz@codeaurora.org> |
[Hexagon] Referencify MachineInstr in HexagonInstrInfo, NFC
llvm-svn: 277220
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Revision tags: llvmorg-3.9.0-rc1 |
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98226e3d |
| 12-Jul-2016 |
Duncan P. N. Exon Smith <dexonsmith@apple.com> |
Hexagon: Avoid implicit iterator conversions, NFC
Avoid implicit iterator conversions from MachineInstrBundleIterator to MachineInstr* in the Hexagon backend, mostly by preferring MachineInstr& over
Hexagon: Avoid implicit iterator conversions, NFC
Avoid implicit iterator conversions from MachineInstrBundleIterator to MachineInstr* in the Hexagon backend, mostly by preferring MachineInstr& over MachineInstr* and switching to range-based for loops.
There's a long tail of API cleanup here, but I'm planning to leave the rest to the Hexagon maintainers. HexagonInstrInfo defines many of its own predicates, and most of them still take MachineInstr*. Some of those actually check for nullptr, so I didn't feel comfortable changing them to MachineInstr& en masse.
llvm-svn: 275142
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Revision tags: llvmorg-3.8.1, llvmorg-3.8.1-rc1 |
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1dbf7a57 |
| 04-Apr-2016 |
Derek Schuff <dschuff@google.com> |
Add MachineFunctionProperty checks for AllVRegsAllocated for target passes
Summary: This adds the same checks that were added in r264593 to all target-specific passes that run after register allocat
Add MachineFunctionProperty checks for AllVRegsAllocated for target passes
Summary: This adds the same checks that were added in r264593 to all target-specific passes that run after register allocation.
Reviewers: qcolombet
Subscribers: jyknight, dsanders, llvm-commits
Differential Revision: http://reviews.llvm.org/D18525
llvm-svn: 265313
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Revision tags: llvmorg-3.8.0, llvmorg-3.8.0-rc3, llvmorg-3.8.0-rc2 |
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14f9535e |
| 21-Jan-2016 |
Krzysztof Parzyszek <kparzysz@codeaurora.org> |
PR26172: unnecessary indirection in HexagonCopyToCombine.cpp
llvm-svn: 258395
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Revision tags: llvmorg-3.8.0-rc1 |
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2a3b2f98 |
| 15-Jan-2016 |
Krzysztof Parzyszek <kparzysz@codeaurora.org> |
[Hexagon] Generate CONST64 when optimizing for size in copy-to-combine
llvm-svn: 257891
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9b7320e6 |
| 15-Jan-2016 |
Krzysztof Parzyszek <kparzysz@codeaurora.org> |
[Hexagon] Handle DBG_VALUE instructions in copy-to-combine
llvm-svn: 257890
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Revision tags: llvmorg-3.7.1, llvmorg-3.7.1-rc2, llvmorg-3.7.1-rc1, llvmorg-3.7.0, llvmorg-3.7.0-rc4, llvmorg-3.7.0-rc3, studio-1.4, llvmorg-3.7.0-rc2, llvmorg-3.7.0-rc1, llvmorg-3.6.2, llvmorg-3.6.2-rc1 |
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56efafc0 |
| 15-Jun-2015 |
Colin LeMahieu <colinl@codeaurora.org> |
[Hexagon] Moving pass declarations out of header and in to implementation files. Removing unused function getSubtargetInfo from HexagonMCCodeEmitter.cpp Removing deletion of copy construction and a
[Hexagon] Moving pass declarations out of header and in to implementation files. Removing unused function getSubtargetInfo from HexagonMCCodeEmitter.cpp Removing deletion of copy construction and assignment operator since parent already deletes it.
llvm-svn: 239744
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Revision tags: llvmorg-3.6.1, llvmorg-3.6.1-rc1 |
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e5689679 |
| 23-Apr-2015 |
Krzysztof Parzyszek <kparzysz@codeaurora.org> |
[Hexagon] Fix compiler warnings in release build
Patch by Aditya Nandakumar.
llvm-svn: 235635
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cd97c985 |
| 22-Apr-2015 |
Krzysztof Parzyszek <kparzysz@codeaurora.org> |
[Hexagon] Use A2_tfrsi for constant pool and jump table addresses
llvm-svn: 235535
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Revision tags: llvmorg-3.5.2, llvmorg-3.5.2-rc1 |
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2efa2d01 |
| 09-Mar-2015 |
Colin LeMahieu <colinl@codeaurora.org> |
[Hexagon] Reapply r231699. Remove assumption that second operand is an immediate when checking if A2_tfrsi is combinable.
llvm-svn: 231710
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