Combine the code to build VLDM and VSTM instructions, since they are
mostly the same.

llvm-svn: 98402

Tidy up. No functional changes.

llvm-svn: 98398

pr6480: Don't try producing ld/st-multiple instructions when the address is
an undef value. This is only going to come up for bugpoint-reduced tests --
correct programs will not access memory at und

pr6480: Don't try producing ld/st-multiple instructions when the address is
an undef value. This is only going to come up for bugpoint-reduced tests --
correct programs will not access memory at undefined addresses -- so it's not
worth the effort of doing anything more aggressive.

llvm-svn: 97745

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Stay away from str <undef> in ARMLoadStoreOpt. This pass does not understand
<undef> operands, and can cause scavenger failures when it translates
<kill,undef> to <kill>.

llvm-svn: 97046

Load / store multiple instructions cannot load / store sp. Sorry, can't come up with a reasonable test case.

llvm-svn: 96023

Don't fold insufficiently aligned ldr/str into ldm/stm instructions.

An unaligned ldr causes a trap, and is then emulated by the kernel with
awesome performance. The darwin kernel does not emulate u

Don't fold insufficiently aligned ldr/str into ldm/stm instructions.

An unaligned ldr causes a trap, and is then emulated by the kernel with
awesome performance. The darwin kernel does not emulate unaligned ldm/stm
Thumb2 instructions, so don't generate them.

This fixes the miscompilation of Multisource/Applications/JM/lencod for Thumb2.

Generating unaligned ldr/str pairs from a 16-bit aligned memcpy is probably
also a bad idea, but that is beyond the scope of this patch.

llvm-svn: 93393

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Move kill flags when the same register occurs more than once in a sequence.

llvm-svn: 92058

Handle undef operands properly.

llvm-svn: 92054

Make insert position available to MergeOpsUpdate.
Rearrange arguments.
No functional changes

llvm-svn: 92053

Perform kill flag calculations in new method. No functional changes.

llvm-svn: 92052

Move repeated code to a new method. No functional change.

llvm-svn: 92051

Fix a bunch of little errors that Clang complains about when its being pedantic

llvm-svn: 91764

improve portability to avoid conflicting with std::next in c++'0x.
Patch by Howard Hinnant!

llvm-svn: 90365

When expanding t2STRDi8 r, r to two stores, add kill markers correctly.

llvm-svn: 88734

Use Unified Assembly Syntax for the ARM backend.

llvm-svn: 86494

Remove includes of Support/Compiler.h that are no longer needed after the
VISIBILITY_HIDDEN removal.

llvm-svn: 85043

Remove VISIBILITY_HIDDEN from class/struct found inside anonymous namespaces.
Chris claims we should never have visibility_hidden inside any .cpp file but
that's still not true even after this commit

Remove VISIBILITY_HIDDEN from class/struct found inside anonymous namespaces.
Chris claims we should never have visibility_hidden inside any .cpp file but
that's still not true even after this commit.

llvm-svn: 85042

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Load / store multiple was missing opportunites when the load / store bundles are at the end of the bb. Test case is already in, the bug is exposed by subsequent commit.

llvm-svn: 84842

Change ld/st multiples to explicitly model the writeback to base register. This fixes most of the -ldstopti-before-sched2 regressions.

llvm-svn: 83191

Fix PR4687. Pre ARMv5te does not support ldrd / strd. Patch by John Tytgat.

llvm-svn: 83058

Enable pre-regalloc load / store multiple pass for Thumb2.

llvm-svn: 82893

Add comment.

llvm-svn: 82836

Code clean up and prepare for Thumb2 support. No functionality changes.

llvm-svn: 82805

Improve MachineMemOperand handling.
- Allocate MachineMemOperands and MachineMemOperand lists in MachineFunctions.
This eliminates MachineInstr's std::list member and allows the data to be
cre

Improve MachineMemOperand handling.
- Allocate MachineMemOperands and MachineMemOperand lists in MachineFunctions.
This eliminates MachineInstr's std::list member and allows the data to be
created by isel and live for the remainder of codegen, avoiding a lot of
copying and unnecessary translation. This also shrinks MemSDNode.
- Delete MemOperandSDNode. Introduce MachineSDNode which has dedicated
fields for MachineMemOperands.
- Change MemSDNode to have a MachineMemOperand member instead of its own
fields with the same information. This introduces some redundancy, but
it's more consistent with what MachineInstr will eventually want.
- Ignore alignment when searching for redundant loads for CSE, but remember
the greatest alignment.

Target-specific code which previously used MemOperandSDNodes with generic
SDNodes now use MemIntrinsicSDNodes, with opcodes in a designated range
so that the SelectionDAG framework knows that MachineMemOperand information
is available.

llvm-svn: 82794

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Update register class references to use the global constant ARM::*RegisterClass names.

llvm-svn: 81556